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TMS320F Datasheet(PDF) 115 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 115 Page - Texas Instruments |
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115 / 389 page ![]() How To Use the Instruction Descriptions 7-15 Assembly Language Instructions The field called dma contains the value dma, which is defined in the operands category. The contents of the fields ARU, N, and NAR are derived from the op- erands ind and n but do not directly correspond to those operands; therefore, a note directs you to the appropriate section for more details. 7.2.4 Execution The execution category presents an instruction operation sequence that de- scribes the processing that takes place when the instruction is executed. If the execution event or events depend on the addressing mode used, the execu- tion category specifies which events are associated with which addressing modes. Here are notations used in the execution category: (r) The content of register or location r. Example: (ACC) represents the value in the accumulator. x → y Value x is assigned to register or location y. Example: (data-memory address) → ACC means: The content of the specified data-memory address is put into the accumulator. r(n:m) Bits n through m of register or location r. Example: ACC(15:0) represents bits 15 through 0 of the accumulator. (r(n:m)) The content of bits n through m of register or location r. Example: (ACC(31:16)) represents the content of bits 31 through 16 of the accumulator. nnh Indicates that nn represents a hexadecimal number. 7.2.5 Status Bits The bits in status registers ST0 and ST1 affect the operation of certain instruc- tions and are affected by certain instructions. The status bits category of each instruction description states which of the bits (if any) affect the execution of the instruction and which of the bits (if any) are affected by the instruction. 7.2.6 Description The description category explains what happens during instruction execution and its effect on the rest of the processor or on memory contents. It also dis- cusses any constraints on the operands imposed by the processor or the as- sembler. This description parallels and supplements the information given in the execution category. |
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