TMS320F datasheet(170/389 Pages) TI

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INTR

Software Interrupt

7-70

Syntax

INTR

Operands

Value from 0 to 31 that indicates the interrupt vector location

to branch to

Opcode

Execution

(PC) + 1

→ stack

corresponding interrupt vector location

→ PC

Status Bits

Affects

INTM

This instruction is not affected by INTM.

Description

The processor has locations for 32 interrupt vectors; each location is repre-

sented by a value K from 0 to 31. The INTR instruction is a software interrupt

that transfers program control to the program-memory address specified by

K. The vector at that address then leads to the corresponding interrupt service

routine. Thus, the instruction allows any one of the interrupt service routines

to be executed from your software. For a list of interrupts and their correspond-

ing K values, see Table 5–5 on page 5-15. During execution of the instruction,

the value PC + 1 (the return address) is pushed onto the stack. Neither the

INTM bit nor the interrupt masks affect the INTR instruction. An INTR for the

external interrupts looks exactly like an external interrupt (an interrupt ac-

knowledge is generated, and maskable interrupts are globally disabled by set-

ting INTM = 1).

Words

Cycles for a Single INTR Instruction

ROM

DARAM

SARAM

External

4+3p†

† The processor performs speculative fetching by reading two additional instruction words. If the

PC discontinuity is taken, these two instruction words are discarded.

Example

INTR

;PC + 1 is pushed onto the stack.

;Then control is passed to program

;memory location 6h.

Cycles

TMS320F Datasheet(PDF) 170 Page - Texas Instruments

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