TMS320F datasheet(167/389 Pages) TI

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Idle Until Interrupt

IDLE

7-67

Assembly Language Instructions

Syntax

IDLE

Operands

None

Opcode

Execution

Increment PC, then wait for unmasked or nonmaskable hardware interrupt.

Status Bits

Affected by

INTM

Description

The IDLE instruction forces the program being executed to halt until the CPU

receives a request from an unmasked hardware interrupt (external or internal),

NMI, or reset. Execution of the IDLE instruction causes the ’C24x/’C20x to en-

ter a power-down mode. The PC is incremented once before the ’C24x/ ’C20x

enters power down; it is not incremented during the idle state. On-chip periph-

erals remain active; thus, their interrupts are among those that can wake the

processor.

The idle state is exited by an unmasked interrupt even if INTM is 1. (INTM, the

interrupt mode bit of status register ST0, normally disables maskable inter-

rupts when it is set to 1.) When the idle state is exited by an unmasked inter-

rupt, the CPU’s next action, however, depends on INTM:

- If INTM is 0, the program branches to the corresponding interrupt service

routine.

- If INTM is 1, the program continues executing at the instruction following

the IDLE.

NMI and reset are not maskable; therefore, if the idle state is exited by NMI or

reset, the corresponding interrupt service routine will be executed, regardless

of INTM.

Words

Cycles for a Single IDLE Instruction

ROM

DARAM

SARAM

External

1+p

Example

IDLE

;The processor idles until a hardware reset,

;a hardware NMI, or an unmasked interrupt

;occurs.

Cycles

TMS320F Datasheet(PDF) 167 Page - Texas Instruments

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