VT8235 datasheet(128/145 Pages) VIA

128 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-122-

Device 18 Function 0 LAN Registers

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Offset 0C – Interrupt Status 0 (00h) ................................RW

CRC or Miss Packet Tally Counter Overflow

Set if either counter overflows (both counters are 16

bits)

PCI Bus Error

Set if PCI bus error occurred.

Receive Buffer Link Error

Set when there is not enough buffer space for a

packet requiring multiple buffers.

Transmit Buffer Underflow

Transmit Error (Packet Transmit Aborted)

Set due to excessive collisions (more than 16),

transmit underflow, or transmit data linking error

Receive Error

Set due to CRC error, frame alignment error, FIFO

overflow, or received data linking error

Packet Transmitted Successfully

Packet Received Successfully

Offset 0D – Interrupt Status 1 (00h) ................................RW

General Purpose Interrupt

This bit is set when there is a general purpose

interrupt event (Rx84). This bit is set when any bit in

Rx84 equals one and when its corresponding mask

bit in Rx86 also equals one.

Port State Change (PHY)

Transmit Abort Due to Excessive Collisions

Set when there is a transmit error that is due to

excessive collisions.

Alternatively, Rx0C[3] is set

for all transmit errors.

Receive Buffer Full

Set when there is no more buffer space available in

system memory.

Receive Packet Race

Set when there is not enough room in the FIFO to

receive an additional packet.

Receive FIFO Overflow

Transmit FIFO Underflow

Early Receive Interrupt

Set if a packet is being received and Rx9[0] = 1.

Offset 0E – Interrupt Mask 0 (00h)................................. RW

Bits correspond to the bits in Interrupt Status Register 0. An

interrupt is generated when corresponding bits in both

registers equal 1.

Offset 0F – Interrupt Mask 1 (00h) ................................. RW

Bits correspond to the bits in Interrupt Status Register 1. An

interrupt is generated when corresponding bits in both

registers equal 1.

Offset 17-10 – Multicast Address..................................... RW

The value in this register determines which Multicast

addresses are received.

Offset 1B-18 – RX Address .............................................. RW

This register reports the receive transcriptor address that is

being accessed.

Offset 1F-1C – TX Address.............................................. RW

This register reports the transmit transcriptor address that is

being accessed.

VT8235 Datasheet(PDF) 128 Page - VIA Technologies, Inc.

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