VT8235 datasheet(132/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-126-

Device 18 Function 0 LAN Registers

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Offset 70 – MII Management Port Command (00h) ......RW

MII (PHY) Auto Polling

Disable .................................................. default

Enable

(polling

interval

determined

Rx6C[7:6] )

PHY Read

Every time this bit is set to one, the PHY is read

once. The address read is determined by Rx71[4:0]

and the data is stored in Rx73-72.

PHY Write

Every time this bit is set to one, the PHY is written

once.

The address written is determined by

Rx71[4:0] and the value in Rx73-72 will be written to

the PHY.

Disable .................................................. default

Enable

PHY Direct Programming Mode

Disable (bits 3-0 are ignored) (see bits 6-5) def

Enable (bits 6-5 are ignored) (see bits 2-0)

MDIO Output Enable Indicator

PHY Direct Programming Write Data Out

During direct programming (write), the value in this

bit is written to the PHY every time bit-0 of this

PHY Direct Programming Read Data In.......... RO

During direct programming (read), every time the

“clock” (bit-0) toggles, the value from the PHY is

stored in this bit.

PHY Direct Programming Clock

This bit acts as the clock during direct reads from and

direct writes to the PHY.

Offset 71 – MII Management Port Address (81h) ..........RW

Polling Status

Polling mechanism is busy (polling can’t be

initiated)

Polling mechanism is idle (polling can be

initiated) ................................................default

Polling Type

Poll One Cycle ...................................... default

Auto polling – close the pause function at bit-5

Polling Complete

Polling not complete.............................. default

Polling complete (auto polling data ready)

4-0

MII Management Port Address Bits 4-0

..def = 01h

This field contains the address of the PHY register to

be read or written.

Offset 73-72 – PHY Data...................................................RW

After a PHY read, the data read from the PHY is stored in this

For writes to the PHY, the data to be written is

placed in this register.

Offset 74 – EEPROM Command / Status (00h) ............. RW

EEPROM Program Complete

...............RO, def = 0

Set when EEPROM loading is complete.

EEPROM Embedded Program Enable

........def = 0

When this bit is set, configuration data (in Rx6E, 6F,

74, 78, 79, 7A, and 7B) will start to be programmed

into the EEPROM.

Dynamically Reload EEPROM Content

......def = 0

When this bit toggles, the Ethernet ID (Rx5-0) is

reloaded from EEPROM.

EEPROM Direct Program Mode

Disable ................................................... default

Enable (see bits 3-0)

EEPROM Direct Programming Chip Select

This bit must be set to allow proramming of the

EEPROM using bits 2-0

EEPROM Direct Programming Clock

This bit acts as the clock for direct programming of

the EEPROM.

EEPROM Direct Programming Read Data In . RO

During direct programming (read), the value in this

bit is written to the EEPROM every time bit-2 of this

EEPROM Direct Programming Wr Data Out

During direct programming (write), the value in this

bit is written to the EEPROM every time bit-2 of this

Offset 78 – EEPROM Control (00h) ............................... RW

EEPROM Embedded & Direct Programming

Disable (EEPROM cannot be programmed) def

Enable (allow EEPROM to be programmed)

Extension Clock

Disable ................................................... default

Enable (the clock to the EEPROM is sent prior

to the start of data to allow more time for the

EEPROM to return to the ready state)

5-0

Reserved

........................................always reads 0

VT8235 Datasheet(PDF) 132 Page - VIA Technologies, Inc.

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