VT8235 datasheet(133/145 Pages) VIA

133 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-127-

Device 18 Function 0 LAN Registers

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Offset 79 – Configuration 1 (00h).....................................RW

Transmit Frame Queueing

Enable (frames from the PCI bus can be

queued in the transmit FIFO – a maximum of

2 packets may be queued) ..................... default

Disable

Data Parity Generation and Checking

This bit controls whether PCI parity is enabled.

Enable.................................................... default

Disable

Memory-Read-Line Supported

This bit controls whether PCI Memory-Read-Line is

supported.

Enable.................................................... default

Disable

Transmit FIFO DMA Interleaved to Receiving

FIFO DMA After 32 DW Transaction

This bit controls whether during a transmit, priority

can be given to a receive transaction.

Disable .................................................. default

Enable (during a transmit, if a receive request

is seen, the transmit is paused after 32 DW’s

and priority is given to the receive)

Receive FIFO DMA Interleaved to Transmitting

FIFO DMA After 32 DW Transaction

This bit controls whether during a receive, priority

can be given to a transmit transaction.

Disable .................................................. default

Enable (during a receive, if a transmit request

is seen, the receive is paused after 32 DW’s

and priority is given to the transmit)

Memory Read Wait States

(for ISA only)

None .................................................... default

Insert one wait state 2222

Memory Write Wait States s

(for ISA only)

None .................................................... default

Insert one wait state 2222

Latency Timer

This bit controls whether PCI Delayed Transactions

are enabled.

Disable .................................................. default

Enable

Offset 7A – Configuration 2 (00h) ................................... RW

Reserved

........................................always reads 0

Unused BootROM Address MA

This bit controls whether unused BootROM memory

address bits are tied high.

Not tied high .......................................... default

Tied high

Delayed Transactions for BootROM Memory

Read

This bit controls whether PCI delayed transactions

are enabled.

Disable ................................................... default

Enable

4-0

Reserved

........................................always reads 0

Offset 7B – Configuration 3 (00h) ................................... RW

Memory Mapped I/O Access

Disable ................................................... default

Enable

6-4

Reserved (Do Not Program)

....................default = 0

Backoff Algorithm

Fixed .................................................... default

Random

DEC Capture Effect Solution

Disable ................................................... default

Enable

AMD Capture Effect Solution

Disable ................................................... default

Enable

Backoff Algorithm Optional

Disable ................................................... default

Enable

VT8235 Datasheet(PDF) 133 Page - VIA Technologies, Inc.

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