VT8235 datasheet(131/145 Pages) VIA

131 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-125-

Device 18 Function 0 LAN Registers

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Offset 6C – PHY Address (01h) .......................................RW

7-6

MII Management Polling Timer Interval (Polling

PHY)

00 1024 MDC Clock Cycles ...................... default

01 512 MDC Clock Cycles

10 128 MDC Clock Cycles

11 64 MDC Clock Cycles

MDC is an internal clock with a 960 ns cycle time.

Accelerate MDC Speed

Normal .................................................. default

4x Accelerated

4-0

Extended PHY Device Address.......... default = 01h

Stored from EEPROM during power-up or EEPROM

auto-reload but can be programmed by software

Offset 6D – MII Status (13h) ............................................RW

PHY Reset

PHY reset not asserted .......................... default

PHY reset asserted

6-5

Reserved

........................................ always reads 0

PHY Option

PHY address updated from EEPROM

Use default PHY address of 0001h .......default

PHY Device Received Error

No MII error.......................................... default

MII Error

Reserved

........................................ always reads 0

Link Failure

Link successful

Link unsuccessful (no connection)........default

PHY Speed

100 Mb

10 Mb ....................................................default

Offset 6E – Buffer Control 0 (00h) .................................. RW

7-6

Reserved

........................................always reads 0

5-3

Rx FIFO Threshold Control

000 Determined by Offset 6 Rcv Ctrl Reg.... default

~000 Determined by bits 2-0 of this register

2-0

DMA Length

000 32 bytes

8 DW ................................ default

001 64 bytes

16 DW

010 128 bytes

32 DW

011 256 bytes

64 DW

100 512 bytes

128 DW

101 1024 bytes

256 DW

11x Store & Forward

Offset 6F – Buffer Control 1 (00h) .................................. RW

7-6

Reserved

........................................always reads 0

5-3

Tx FIFO Threshold Control

000 Determined by Rx7 Transmit Control ... default

~000 Determined by this register

2-0

Polling Interval Timer

This field determines the polling interval when TD /

RD Auto-Polling is enabled (Rx09[3]=0).

000 4 PCI Clocks .......................................... default

001 1 PCI Clock

010 2 PCI Clocks

011 8 PCI Clocks

100 16 PCI Clocks

101 32 PCI Clocks

110 64 PCI Clocks

111 128 PCI Clocks

VT8235 Datasheet(PDF) 131 Page - VIA Technologies, Inc.

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