VT8235 datasheet(135/145 Pages) VIA

135 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-129-

Device 18 Function 0 LAN Registers

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Offset 84 – MII Interrupt Status (00h) .........................RWC

The bits in this register correspond to bits in the MII Interrupt

Mask register (Rx86).

An interrupt is generated when

corresponding bits in both registers equal one.

7-4

Reserved (Do Not Program)

.................... default = 0

Transmit Data Write Buffer Queue Race

.... def = 0

Set when write back race for transmit occurs. Write

back race occurs when a new write back is generated

with 2 write backs already queued.

Reserved

........................................ always reads 0

Soft Timer 1 Timeout

............................... default = 0

Soft Timer 0 Timeout

............................... default = 0

All bits above: write 0 to clear the interrupt

Offset 86 – MII Interrupt Mask (00h) .............................RW

The bits in this register correspond to bits in the MII Interrupt

Status register (Rx84).

An interrupt is generated when

corresponding bits in both registers equal one.

7-4

Reserved (Do Not Program)

.................... default = 0

Transmit Shutdown Interrupt Mask

Reserved

........................................ always reads 0

Soft Timer 1 Interrupt Mask

Soft Timer 0 Interrupt Mask

All bits above:

Disable .................................................. default

Enable

Offset 8D-8C – Flash Address.......................................... RW

This register stores the address that is read from or written to

when reading or configuring the BootROM.

15-0 Flash Address [15:0]

.................................default = 0

Offset 8F – Flash Write Data Out ................................... RW

This register stores the data that is written to the BootROM.

7-0

Flash Write Data Out

...............................default = 0

Offset 90 – Flash Read / Write Command...................... RW

7-2

Reserved

........................................always reads 0

Boot ROM Embedded Write Command

......def = 0

Setting this bit initiates a write transaction (data in

Rx8F will be written to the address specified in

Rx8D-8C).

Boot ROM Embedded Read Command

.......def = 0

Setting this bit initiates a read transaction (data in the

address specified in Rx8D-8C will be read and stored

in Rx91).

Offset 91 – Flash Write Data In........................................ RO

This register stores the data that is read from the BootROM.

7-0

Flash Write Data In

..................................default = 0

Offset 93 – Flash Checksum (00h)................................... RW

This register stores the checksum from the BootROM after

programming.

7-0

EEPROM Checksum

...............................default = 0

VT8235 Datasheet(PDF) 135 Page - VIA Technologies, Inc.

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