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4559 Datasheet(PDF) 50 Page - Renesas Technology Corp

Part # 4559
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  148 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4559 Datasheet(HTML) 50 Page - Renesas Technology Corp

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Rev.1.04
Aug 23, 2007
Page 50 of 146
REJ03B0188-0104
4559 Group
(2) Power-on reset
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, set the time for the supply voltage
to rise from 0 V to the minimum voltage of recommended
operating conditions to 100
µs or less.
If the rising time exceeds 100
µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET
pin and system reset is performed.
Fig 50. Power-on reset operation
Note 1. Output latch is set to “1.”
Note 2. The output structure is N-channel open-drain.
Note 3. Pull-up transistor is turned OFF.
100
µs or less
VDD (Note)
Power-on reset
circuit output
Internal reset signal
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Reset
released
Reset
state
Power-on
Table 21 Port state at reset
Name
Function
State
D0
−D4
D0
−D4
High-impedance (Notes 1, 2)
D5/INT
D5
High-impedance (Notes 1, 2)
XCIN/D6
, XCOUT/D7
XCIN
, XCOUT
Sub-clock input
P00/SEG16
−P03/SEG19
P00
−P03
High-impedance (Notes 1, 2, 3)
P10/SEG20
−P13/SEG23
P10
−P13
High-impedance (Notes 1, 2, 3)
P20/SEG24
−P23/SEG27
P20
−P23
High-impedance (Notes 1, 2, 3)
P30/SEG28
−P33/SEG31
P30
−P33
High-impedance (Notes 1, 2, 3)
SEG0/VLC3
−SEG2/VLC1
SEG0
−SEG2
VLC3 (VDD) level
SEG3
−SEG15
SEG3
−SEG15
VLC3 (VDD) level
COM0
−COM3
COM0
−COM3
VLC3 (VDD) level
C/CNTR
C/CNTR
“L” (VSS) level



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