4559 datasheet(7/148 Pages) RENESAS

7 / 148 page

Rev.1.04

Aug 23, 2007

Page 7 of 146

REJ03B0188-0104

4559 Group

DEFINITION OF CLOCK AND CYCLE

• Operation source clock

The operation source clock is the source clock to operate this

product. In this product, the following clocks are used.

• Clock (f(XIN)) by the external ceramic resonator

• Clock (f(XIN)) by the external RC oscillation

• Clock (f(XIN)) by the external input

• Clock (f(RING)) of the on-chip oscillator which is the internal

oscillator

• Clock (f(XCIN)) by the external quartz-crystal oscillation

• System clock (STCK)

The system clock is the basic clock for controlling this product.

The system clock is selected by the clock control register MR

shown as the table below.

• Machine cycle

The machine cycle is the standard cycle required to execute the

instruction.

• Instruction clock (INSTCK)

The instruction clock is the basic clock for controlling CPU. The

instruction clock (INSTCK) is a signal derived by dividing the

system clock (STCK) by 3. The one instruction clock cycle

generates the one machine cycle.

Note 1. The f(RING)/8 is selected after system is released from reset

Table 6

Table Selection of system clock

System clock

Operation mode

MR3

MR2

MR1

MR0

f(STCK) = f(RING)/8

Internal frequency divided by 8 mode

f(STCK) = f(RING)/4

Internal frequency divided by 4 mode

f(STCK) = f(RING)/2

Internal frequency divided by 2 mode

f(STCK) = f(RING)

Internal frequency through mode

f(STCK) = f(XIN)/8

High-speed frequency divided by 8 mode

f(STCK) = f(XIN)/4

High-speed frequency divided by 4 mode

f(STCK) = f(XIN)/2

High-speed frequency divided by 2 mode

f(STCK) = f(XIN)

High-speed through mode

f(STCK) = f(XCIN)/8

Low-speed frequency divided by 8 mode

f(STCK) = f(XCIN)/4

Low-speed frequency divided by 4 mode

f(STCK) = f(XCIN)/2

Low-speed frequency divided by 2 mode

f(STCK) = f(XCIN)

Low-speed through mode

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