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4559 Datasheet(PDF) 60 Page - Renesas Technology Corp |
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4559 Datasheet(HTML) 60 Page - Renesas Technology Corp |
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60 / 148 page  Rev.1.04 Aug 23, 2007 Page 60 of 146 REJ03B0188-0104 4559 Group Table 27 Interrupt control register Note 1. “R” represents read enabled, and “W” represents write enabled. Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Interrupt control register I1 at reset : 00002 at power down : state retained R/W TAI1/TI1A I13 INT pin input control bit (Note 2) 0 INT pin input disabled 1 INT pin input enabled I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 2) 0 Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level 1 Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level I11 INT pin edge detection circuit control bit 0 One-sided edge detected 1 Both edges detected I10 INT pin timer 1 count start synchronous circuit selection bit 0 Timer 1 count start synchronous circuit not selected 1 Timer 1 count start synchronous circuit selected |
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