4559 datasheet(83/148 Pages) RENESAS

83 / 148 page

Rev.1.04

Aug 23, 2007

Page 83 of 146

REJ03B0188-0104

4559 Group

INSTRUCTIONS

Each instruction is described as follows;

1. Index list of instruction function

2. Machine instructions (index by alphabet)

3. Machine instructions (index by function)

4. Instruction code table

The symbols shown below are used in the following list of

instruction function and the machine instructions.

Note 1. The 4559 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased

by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if

the TABP p, RT, or RTS instruction is skipped.

SYMBOL

Symbol

Contents

Symbol

Contents

R2H

Timer 2 reload register (8 bits)

RLC

Timer LC reload register (4 bits)

Prescaler

Timer 1

Interrupt control register V1 (4 bits)

Timer 2

Interrupt control register V2 (4 bits)

TLC

Timer LC

Interrupt control register I1 (4 bits)

T1F

Timer 1 interrupt request flag

Timer control register PA (1 bit)

T2F

Timer 2 interrupt request flag

Timer control register W1 (4 bits)

T3F

Timer 3 interrupt request flag

Timer control register W2 (4 bits)

WDF1

Watchdog timer flag

Timer control register W3 (4 bits)

WEF

Watchdog timer enable flag

Timer control register W4 (4 bits)

INTE

Interrupt enable flag

Clock control register MR (4 bits)

EXF0

External 0 interrupt request flag

Clock control register RG (3 bits)

VDF

Voltage drop detection circuit flag

LCD control register L1 (4 bits)

Power down flag

LCD control register L2 (4 bits)

Port D (8 bits)

LCD control register L3 (4 bits)

Port P0 (4 bits)

LCD control register C1 (4 bits)

Port P1 (4 bits)

LCD control register C2 (4 bits)

Port P2 (4 bits)

LCD control register C3 (4 bits)

Port P3 (4 bits)

Key-on wakeup control register K0 (4 bits)

Port C (1 bit)

Key-on wakeup control register K1 (4 bits)

INT

INT pin (1 bit)

Key-on wakeup control register K2 (4 bits)

Key-on wakeup control register K3 (4 bits)

Hexadecimal variable

PU0

Pull-up control register PU0 (4 bits)

Hexadecimal variable

PU1

Pull-up control register PU1 (4 bits)

Hexadecimal variable

PU2

Pull-up control register PU2 (4 bits)

Hexadecimal variable

PU3

Pull-up control register PU3 (4 bits)

Hexadecimal constant

FR0

Port output structure control register FR0 (4 bits)

Hexadecimal constant

FR1

Port output structure control register FR1 (4 bits)

Hexadecimal constant

FR2

Port output structure control register FR2 (4 bits)

A3 A2 A1 A0

Binary notation of hexadecimal variable A

(same for others)

FR3

Port output structure control register FR3 (4 bits)

←

Direction of data movement

(

)

Contents of registers and memories

−

Negate, Flag unchanged after executing instruction

Data pointer (10 bits)

(It consists of registers X, Y, and Z)

M (DP)

RAM address pointed by the data pointer

Label indicating address a6 a5 a4 a3 a2 a1 a0

Program counter (14 bits)

p, a

Label indicating address a6 a5 a4 a3 a2 a1 a0 in page

p6 p5 p4 p3 p2 p1 p0

PCH

High-order 7 bits of program counter

PCL

Low-order 7 bits of program counter

Stack register (14 bits

× 8)

C+x

Hex. C + Hex. number x (also same for others)

Stack pointer (3 bits)

Decision of state shown before “?”

Carry flag

← →

Data exchange between a register and memory

UPTF

High-order bit reference enable flag

RPS

Prescaler reload register (8 bits)

Timer 1 reload register (8 bits)

R2L

Timer 2 reload register (8 bits)

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