4559 datasheet(57/148 Pages) RENESAS

57 / 148 page

Rev.1.04

Aug 23, 2007

Page 57 of 146

REJ03B0188-0104

4559 Group

Fig 56. State transition

Fig 57. Set source and clear source of the P flag

Fig 58. Start condition identified example using the

SNZP instruction

Clock operating mode

f(RING): stop

f(XIN): stop

f(XCIN): operating

Key-on wakeup

(Stabilizing time c )

execution

RAM back-up mode

High-speed mode

Operation source clock:

f(XCIN)

MR1,MR0

Low-speed mode

execution

Key-on wakeup

(Stabilizing time e )

execution

(Stabilizing time e )

(Stabilizing time c )

CRCK instruction no execution

Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times.

Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio X 171) times.

Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.

Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.

Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.

execution

Key-on wakeup

(Stabilizing time b )

execution

(Stabilizing time b )

(Stabilizing time a )

Operation state

Operation source clock:

f(RING)

execution

Key-on wakeup

(Stabilizing time d )

execution

(Stabilizing time d )

f(RING): stop

f(XIN): stop

f(XCIN): stop

CRCK instruction execution

MR1,MR0

Internal mode

Notes

EPOF + POF instruction

Key-on wakeup

Timer 3 underflow

Key-on wakeup

Timer 3 underflow

Key-on wakeup

Timer 3 underflow

Key-on wakeup

Timer 3 underflow

EPOF + POF 2 instruction

EPOF + POF 2

instruction

EPOF + POF 2 instruction

execution

‹

1: Selection of the system clock by the clock control registers MR and RG is state retained at power down.

The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG

before transition to the power down state.

and generate the wait time until the oscillation is stabilized, and then, switch the system clock.

6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,

If the CRCK instruction is not executed, the ceramic resonator is selected as the main clock f(XIN).

5: When the RC oscillation circuit is used, executing the CRCK instruction is required.

•Mainclock (f(XIN)) and Sub-clock (f(XCIN)) are valid.

• A ceramic resonator is selected as the main clock (f(XIN)).

4: The state after system is released from reset;

3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.

2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.

Ceramic resonator

RC oscillation

Operation state

Operation source clock: f(XIN)

Operation state

Operation source clock: f(XIN)

On-chip oscillator

Operation state

Quartz-crystal oscillation

7: The Sub-clock (quartz-crystal oscillation) is operating except in state D.

Power downflagP

POF or

POF2

instruction

Reset input

Set source

Clear source

System reset

•• •• • • •

• • ••• •

EPOF instruction +

POF or

POF2

instruction

EPOF instruction +

Program start

P= “1”

Warm start

Cold start

T3F =

Return from

timer 3 underflow

Return from

external wakeup signal

“1”

Yes

SNZT3

instruction

SNZP

instruction

4559 Datasheet(PDF) 57 Page - Renesas Technology Corp

4559 Datasheet(HTML) 57 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL