4559 datasheet(25/148 Pages) RENESAS

25 / 148 page

Rev.1.04

Aug 23, 2007

Page 25 of 146

REJ03B0188-0104

4559 Group

(6) Interrupt control registers

• Interrupt control register V1

Interrupt enable bits of external 0, timer 1 and timer 2 are

assigned to register V1. Set the contents of this register through

be used to transfer the contents of register V1 to register A.

• Interrupt control register V2

The timer 3 interrupt enable bit are assigned to register V2. Set

the contents of this register through register A with the TV2A

instruction. The TAV2 instruction can be used to transfer the

contents of register V2 to register A.

Note 1.“R” represents read enabled, and “W” represents write enabled.

(7) Interrupt sequence

Interrupts occur only when the respective INTE flag, interrupt

enable bits (V10, V12, V13, V30), and interrupt request flag are

set to “1.” The interrupt occurs two or three cycles after the cycle

where all the above three conditions are satisfied.

The interrupt occurs after three machine cycles if instructions

other than one-cycle instruction are executed when the

conditions are satisfied (Refer to Figure 27).

Table 13 Interrupt control registers

Interrupt control register V1

at reset : 00002

at power down : 00002

R/W

TAV1/TV1A

V13

Timer 2 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

V12

Timer 1 interrupt enable bit

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

V11

Not used

This bit has no function, but read/write is enabled.

V10

External 0 interrupt enable bit

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

Interrupt control register V2

at reset : 00002

at power down : 00002

R/W

TAV2/TV2A

V23

Not used

This bit has no function, but read/write is enabled.

V22

Not used

This bit has no function, but read/write is enabled.

V21

Not used

This bit has no function, but read/write is enabled.

V20

Timer 3 interrupt enable bit

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

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