4559 datasheet(64/148 Pages) RENESAS

64 / 148 page

Rev.1.04

Aug 23, 2007

Page 64 of 146

REJ03B0188-0104

4559 Group

(7) Clock control register MR

(frequency division of system clock). Set the contents of this

addition, the TAMR instruction can be used to transfer the

contents of register MR to register A.

(8) Clock control register RG

the contents of this register through register A with the TRGA

instruction.

Note 1. R” represents read enabled, and “W” represents write enabled.

Note 2. The stopped clock cannot be selected for system clock.

Note 3. “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.

Note 4. The oscillation circuit selected for system clock cannot be stopped.

Table 28 Clock control registers

Clock control register MR

at reset : 11002

at power down : state retained

R/W

TAMR/TMRA

MR3

Operation mode selection bits

MR3 MR2

Operation mode

Through mode

Frequency divided by 2 mode

MR2

Frequency divided by 4 mode

Frequency divided by 8 mode

MR1

System clock selection bits (Note 2)

MR1 MR0

System clock

f(RING)

MR0

f(XIN)

f(XCIN)

Not available (Note 3)

Clock control register RG

at reset : 0002

at power down : state retained

TRGA

RG2

Sub-clock (f(XCIN)) control bit (Note 4)

Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected

Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected

RG1

Main-clock (f(XIN)) control bit (Note 4)

Main clock (f(XIN)) oscillation available

Main clock (f(XIN)) oscillation stop

RG0

On-chip oscillator (f(RING)) control bit

(Note 4)

On-chip oscillator (f(RING)) oscillation available

On-chip oscillator (f(RING)) oscillation stop

4559 Datasheet(PDF) 64 Page - Renesas Technology Corp

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