4559 datasheet(75/148 Pages) RENESAS

75 / 148 page

Rev.1.04

Aug 23, 2007

Page 75 of 146

REJ03B0188-0104

4559 Group

CONTROL REGISTERS

Note 1. “R” represents read enabled, and “W” represents write enabled.

Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.

Interrupt control register V1

at reset : 00002

at power down : 00002

R/W

TAV1/TV1A

V13

Timer 2 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

V12

Timer 1 interrupt enable bit

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

V11

Not used

This bit has no function, but read/write is enabled.

V10

External 0 interrupt enable bit

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

Interrupt control register V2

at reset : 00002

at power down : 00002

R/W

TAV2/TV2A

V23

Not used

This bit has no function, but read/write is enabled.

V22

Not used

This bit has no function, but read/write is enabled.

V21

Not used

This bit has no function, but read/write is enabled.

V20

Timer 3 interrupt enable bit

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

Interrupt control register I1

at reset : 00002

at power down : state retained

R/W

TAI1/TI1A

I13

INT pin input control bit (Note 2)

INT pin input disabled

INT pin input enabled

I12

Interrupt valid waveform for INT pin/

return level selection bit (Note 2)

Falling waveform (“L” level of INT pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

I11

INT pin edge detection circuit control bit

One-sided edge detected

Both edges detected

I10

INT pin timer 1 count start synchronous

circuit selection bit

Timer 1 count start synchronous circuit not selected

Timer 1 count start synchronous circuit selected

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