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4559 Datasheet(PDF) 20 Page - Renesas Technology Corp |
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4559 Datasheet(HTML) 20 Page - Renesas Technology Corp |
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20 / 148 page ![]() Rev.1.04 Aug 23, 2007 Page 20 of 146 REJ03B0188-0104 4559 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 18). Make sure that the PCH does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 19). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 20). •Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these registers. Fig 18. Program counter (PC) structure Fig 19. Data pointer (DP) structure Fig 20. SD instruction execution example a3 a2 a1 a0 a6 a5 a4 PCH Specifying page Program counter (PC) p3 p2 p1 p0 p6 p5 p4 PCL Specifying address Register Y (4) Data pointer (DP) X2 X1 X0 Y3 Z1 Z0 X3 Y2 Y1 Y0 Register X (4) Register Z (2) Specifying RAM digit Specifying RAM file Specifying RAM file group Specifying bit position 0 0 0 1 Register Y (4) Set D3 D2 1 D1 D0 Port D output latch |
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