4559 datasheet(18/148 Pages) RENESAS

18 / 148 page

Rev.1.04

Aug 23, 2007

Page 18 of 146

REJ03B0188-0104

4559 Group

FUNCTION BLOCK OPERATIONS

CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as

4-bit data addition, comparison, AND operation, OR operation,

and bit manipulation.

(2) Register A and carry flag

exchange, and I/O operation.

Carry flag CY is a 1-bit flag that is set to “1” when there is a

carry with the AMC instruction (Figure 12).

It is unchanged with both A n instruction and AM instruction.

The value of A0 is stored in carry flag CY with the RAR

instruction (Figure 13).

Carry flag CY can be set to “1” with the SC instruction and

cleared to “0” with the RC instruction.

(3) Registers B and E

data, and for 8-bit data transfer together with register A.

transfer with register B used as the high-order 4 bits and register

A as the low-order 4 bits (Figure 14).

returned from the power down mode. Accordingly, set the initial

value.

(4) Register D

It is used to store a 7-bit ROM address together with register A

and is used as a pointer within the specified page when the TABP

p, BLA p, or BMLA p instruction is executed (Figure 15).

Also, when the TABP p instruction is executed at UPTF flag =

“1”, the high-order 2 bits of ROM reference data is stored to the

low-order 2 bits of register D, the high-order 1 bit of register D is

“0”.

When the TABP p instruction is executed at UPTF flag = “0”, the

contents of register D remains unchanged. The UPTF flag is set

to “1” with the SUPT instruction and cleared to “0” with the

RUPT instruction.

The initial value of UPTF flag is “0”.

returned from the power down mode. Accordingly, set the initial

value.

Fig 12. AMC instruction execution example

Fig 13. RAR instruction execution example

Fig 14. Registers A, B and register E

Fig 15. TABP p instruction execution example

(CY)

(M(DP))

(A)

Addition

ALU

<Carry>

<Clear>

RC instruction

<Set>

SC instruction

A3 A2 A1 A0

RAR instruction

CY A3 A2 A1

TABE instruction

TEAB instruction

A3 A2 A1 A0

TAB instruction

E3 E2 E1 E0

E7 E6 E5 E4

B3 B2 B1 B0

A3 A2 A1 A0

TBA instruction

B3 B2 B1 B0

A3 A2 A1 A0

DR2 DR1 DR0

PCL

Low-order 2 bits

Middle-order 2 bits

ROM

Field value p

The contents

of register D

Specifying address

TABP p

instruction

PCH

The contents

of register A

High-order 2 bits

Flag UPTF = 1;

High-order 2 bits of reference data is transferred to the low-order 2

bits of register D.

“0” is stored to the high-order 1 bit of register D.

Flag UPTF = 0;

Data is not transferred to register D.

4559 Datasheet(PDF) 18 Page - Renesas Technology Corp

4559 Datasheet(HTML) 18 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL