4559 datasheet(55/148 Pages) RENESAS

55 / 148 page

Rev.1.04

Aug 23, 2007

Page 55 of 146

REJ03B0188-0104

4559 Group

POWER DOWN FUNCTION

The 4559 Group has 2-type power down functions.

System enters into each power down state by executing the

following instructions.

• Clock operating mode ................. EPOF and POF instructions

• RAM back-up mode ................... EPOF and POF2 instructions

When the EPOF instruction is not executed before the POF or

POF2 instruction is executed, these instructions are equivalent to

the NOP instruction.

(1) Clock operating mode

The following functions and states are retained.

•RAM

• Reset circuit

•XCIN–XCOUT oscillation

•LCD display

•Timer 3

(2) RAM back-up mode

The following functions and states are retained.

•RAM

• Reset circuit

(3) Warm start condition

The system returns from the power down state when;

• External wakeup signal is input

• Timer 3 underflow occurs

in the power down mode.

In either case, the CPU starts executing the software from

address 0 in page 0. In this case, the P flag is “1.”

(4) Cold start condition

The CPU starts executing the software from address 0 in page 0

when;

• external “L” level is input to RESET pin,

• execute system reset instruction (SRST instruction)

• reset by watchdog timer is performed

• reset by internal power-on reset, or

• reset by the voltage drop detection circuit is performed.

In this case, the P flag is “0.”

(5) Identification of the start condition

Warm start or cold start can be identified by examining the state

of the power down flag (P) with the SNZP instruction. The warm

start condition from the clock operating mode can be identified

by examining the state of T3F flag.

Note 1. “O” represents that the function can be retained, and “

×”

represents that the function is initialized.

Registers and flags other than the above are undefined at

power down mode, and set an initial value after returning.

Note 2. The stack pointer (SP) points the level of the stack

Note 3. The state of the timer is undefined.

Note 4. Initialize the WDF1 flag with the WRST instruction, and

then go into the power down state.

Note 5. LCD is turned off.

Note 6. When the SVDE instruction is executed, this function is

valid at power down.

Note 7. In the power down mode, C/CNTR pin outputs “L” level.

However, when the CNTR input is selected (W11,

W10=“11”), C/CNTR pin is in an input enabled state

(output = high-impedance).

Other ports retain their respective output levels.

Table 23 Functions and states retained at power down

mode

Function

Power down mode

Clock

operating

RAM

back-up

Program counter (PC), registers A, B,

carry flag (CY), stack pointer (SP)

(Note 2)

××

Contents of RAM

Interrupt control registers V1, V2

××

Interrupt control registers I1

Selected oscillation circuit

Clock control register MR, RG

Timer 1, Timer 2 functions

(Note 3)

Timer 3 function

(Note 3)

Timer LC function

(Note 3)

Watchdog timer function

× (Note 4) × (Note 4)

Timer control registers PA, WA

××

Timer control registers W1, W3, W4

LCD display function

(Note 5)

LCD control registers L1 to L3, C1 to

Voltage drop detection circuit

(Note 6)

Port level

(Note 7)

Key-on wakeup control registers K0 to

Pull-up control registers PU0, PU1

Port output structure control registers

FR0 to FR2

External interrupt request flags (EXF0)

××

Timer interrupt request flags (T1F, T2F)

(Note 3)

Timer interrupt request flag (T3F)

(Note 3)

Interrupt enable flag (INTE)

××

Voltage drop detection circuit flag

(VDF)

××

Watchdog timer flags (WDF1, WDF2)

× (Note 4) × (Note 4)

Watchdog timer enable flag (WEF)

× (Note 4) × (Note 4)

4559 Datasheet(PDF) 55 Page - Renesas Technology Corp

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