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4559 Datasheet(PDF) 32 Page - Renesas Technology Corp |
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4559 Datasheet(HTML) 32 Page - Renesas Technology Corp |
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32 / 148 page ![]() Rev.1.04 Aug 23, 2007 Page 32 of 146 REJ03B0188-0104 4559 Group Fig 33. Timers structure (1) XIN ORCLK XIN ORCLK W21 Timer 2 (8) Reload register R2L (8) Register B (TAB2) (T2AB) Register A (T2AB) (T2AB) (TAB2) Timer 2 interrupt 11 10 01 00 W11, W10 PWMOUT ORCLK W12 W40 0 1 Timer 1 (8) Reload register R1 (8) Register B (TAB1) (T1AB) Register A (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt Timer 1 underflow signal (T1UDF) T3UDF 00 01 10 11 MR3, MR2 Division circuit Divided by 8 Divided by 4 Divided by 2 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) Prescaler (8) PA0 Reload register RPS (8) Register B (TABPS) (TPSAB) Register A (TPSAB) (TPSAB) (TABPS) (TR1AB) 10 01 (CRCK) MR1, MR0 On-chip oscillator Quartz-crystal oscillation XCIN Multi- plexer Ceramic resonance RC oscillation D5/INT I13 I12 0 1 I11 0 1 One-sided edge detection circuit Both edges detection circuit S R Q I10 W13 T1UDF C/CNTR W11 W10 PWMOUT Q D R T W12 W41 T1UDF I10 1 0 Port C output W20 0 1 Reload register R2H (8) Register B Register A Reload control circuit “H” interval expansion W22 1 0 (T2R2L) (T2HAB) T2F Q R T W23 PWMOD Data is set automatically from each reload register when timer underflows (auto-reload function). 1/2 00 |
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