4559 datasheet(28/148 Pages) RENESAS

28 / 148 page

Rev.1.04

Aug 23, 2007

Page 28 of 146

REJ03B0188-0104

4559 Group

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a

valid waveform is input to D5/INT pin.

The valid waveforms causing the interrupt must be retained at

their level for 4 clock cycles or more of the system clock (Refer

to Figure 27).

The state of EXF0 flag can be examined with the skip instruction

(SNZ0). Use the interrupt control register V1 to select the

interrupt or the skip instruction. The EXF0 flag is cleared to “0”

when an interrupt occurs or when the next instruction is skipped

with the skip instruction.

• External 0 interrupt activated condition

External 0 interrupt activated condition is satisfied when a

valid waveform is input to D5/INT pin.

The valid waveform can be selected from rising waveform,

falling waveform or both rising and falling waveforms. An

example of how to use the external 0 interrupt is as follows.

(1) Set the bit 3 of register I1 to “1” for the INT pin to be in the

input enabled state.

(2) Select the valid waveform with the bits 1 and 2 of register

I1.

(3) Clear the EXF0 flag to “0” with the SNZ0 instruction.

(4) Set the NOP instruction for the case when a skip is

performed with the SNZ0 instruction.

(5) Set both the external 0 interrupt enable bit (V10) and the

INTE flag to “1.”

The external 0 interrupt is now enabled. Now when a valid

waveform is input to the D5/INT pin, the EXF0 flag is set to “1”

and the external 0 interrupt occurs.

(2) External interrupt control registers

(1) Interrupt control register I1

interrupt. Set the contents of this register through register A

with the TI1A instruction. The TAI1 instruction can be used

to transfer the contents of register I1 to register A.

Note 1.“R” represents read enabled, and “W” represents write enabled.

Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.

Table 15 External interrupt control register

Interrupt control register I1

at reset : 00002

at power down : state retained

R/W

TAI1/TI1A

I13

INT pin input control bit (Note 2)

INT pin input disabled

INT pin input enabled

I12

Interrupt valid waveform for INT pin/

return level selection bit (Note 2)

Falling waveform (“L” level of INT pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

I11

INT pin edge detection circuit control bit

One-sided edge detected

Both edges detected

I10

INT pin timer 1 count start synchronous

circuit selection bit

Timer 1 count start synchronous circuit not selected

Timer 1 count start synchronous circuit selected

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