PM7346 datasheet(113/419 Pages) PMC

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PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 92

Bit

Type

Function

Default

Bit 7

R/W

STATSEL[2]

Bit 6

R/W

STATSEL[1]

Bit 5

R/W

STATSEL[0]

Bit 4

R/W

TXMFPI

Bit 3

R/W

TXGAPEN

Bit 2

R/W

RXGAPEN

Bit 1

R/W

TXMFPO

Bit 0

R/W

RXMFPO

RXMFPO:

The RXMFPO bit controls which of the outputs RMFPO[4:1] or RFPO[4:1] is

valid. If RXMFPO is a logic 1, then RMFPO[4:1] will be available. If RXMFPO

is a logic 0, then RFPO[4:1] will be available. This bit has effect only if the

FRMRONLY bit in the S/UNI-QJET Configuration 1 register is a logic 1.

TXMFPO:

The TXMFPO bit controls which of the outputs TMFPO[4:1] or TFPO[4:1] is

valid. If TXMFPO is a logic 1, then TMFPO[4:1] will be available. If TXMFPO

is a logic 0, then TFPO[4:1] will be available. This bit has effect only if the

FRMRONLY bit in the S/UNI-QJET Configuration 1 register is a logic 1. The

TXGAPEN bit takes precedence over the TXMFPO bit.

RXGAPEN:

The RXGAPEN bit configures the S/UNI-QJET to enable the RGAPCLK[x]

outputs. When RXGAPEN is a logic 1, then the RGAPCLK[x] output is

enabled. When RXGAPEN is a logic 0, then the RSCLK[x] output is enabled.

The FRMRONLY register bit must be a logic 1 for RXGAPEN to have effect.

TXGAPEN:

The TXGAPEN bit configures the S/UNI-QJET to enable the TGAPCLK[x]

outputs. When TXGAPEN is a logic 1, the TGAPCLK[x] output is enabled.

When TXGAPEN is a logic 0, then either the TFPO[x] or TMFPO[x] output is

enabled, depending on the setting of the TXMFPO register bit. The

FRMRONLY register bit must be a logic 1 for TXGAPEN to have effect.

PM7346 Datasheet(PDF) 113 Page - PMC-Sierra, Inc

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