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PM7346 Datasheet(PDF) 169 Page - PMC-Sierra, Inc

Part # PM7346
Description  SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PDF  419 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7346 Datasheet(HTML) 169 Page - PMC-Sierra, Inc

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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 148
line code violations on the RLCV input. When a logic 0 is written to UNI, the
S/UNI-QJET accepts B3ZS-encoded dual-rail data on RPOS and RNEG.
M3O8:
The M3O8 bit controls the DS3 out of frame decision criteria. When a logic 1
is written to M3O8, DS3 out of frame is declared when 3 of 8 framing bits
(F-bits) are in error. When a logic 0 is written to M3O8, the 3 of 16 framing
bits in error criteria is used, as recommended in ANSI T1.107
MBDIS:
The MBDIS bit disables the use of M-bit errors as a criteria for losing frame
alignment. When MBDIS is set to logic 1, M-bit errors are disabled from
causing an OOF; the loss of frame criteria is based solely on the number of
F-bit errors selected by the M3O8 bit. When MBDIS is set to logic 0, errors in
either M-bits or F-bits are enabled to cause an OOF. When MBDIS is logic 0,
an OOF can occur when one or more M-bit errors occur in 3 out of 4
consecutive M-frames, or when the F-bit error ratio selected by the M3O8 bit
is exceeded.
FDET:
The FDET bit selects the fast detection timing for AIS, IDLE and RED. When
FDET is set to logic 1, the AIS, IDLE, and RED detection time is 2.23 ms;
when FDET is set to logic 0, the detection time is 13.5 ms.
AISPAT:
The AISPAT bit controls the pattern used to detect the alarm indication signal
(AIS). When a logic 1 is written to AISPAT, the AIS detection algorithm checks
that a framed DS3 signal containing the repeating pattern 1010... is present.
The C-bits are checked for the value specified by the AISC bit setting. When
a logic 0 is written to AISPAT, the AIS detection algorithm is determined solely
by the settings of AISC and AISONES register bits (see bit mapping table in
the Additional Configuration Register description).



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