ACT2861 datasheet(73/97 Pages) QORVO

73 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

73 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

REG 0x05: Faults 1 (Read only) (VM)

Bit

Name

Description

Comment

nIRQ_Clear

0: Normal Status

1: Clear IRQ output

Write this bit to 1 to clear the IRQ output. The bit will self-

clear to a 0 once the write occurs. If a fault still occurs, then

nIRQ pin may stay asserted low.

output.

CHG_TIMER_EXPIR

0: No Fault

1: Timer Expired

The VBAT LOW or Fast Charge Safety timer has expired –

Charge Only Mode.

Read to clear this latching fault bit.

Note: Reading this bit will not reset the fault timers. If the

fault timers are high, this bit will get set again immediately

after the read.

See the Safety Timer section on how to reset the Safety

Timers.

CHG_VBAT_OV

0: No Fault

1: VBAT OV

VBAT Overvoltage protection Charge Mode.

Read to clear this latching fault bit.

VREG_OC_UVLO

0: No Fault

1: VREG OC or UVLO

VREG_LDO Overcurrent or UVLO Charge Mode or OTG

Mode.

Read to clear this latching fault bit.

The fault mask bits DIS_CHG_VREG_FLT and

DIS_OTG_VREG_FLT registers do not affect this fault bit. It

will always get indicated here to notify the user.

Note: There is a 100msec restart delay for OC faults on the

VREG LDO, so the delay must expire before this bit can be

reset with a read to clear.

TSD

0: No Fault

1: Over Temperature

Die Thermal Shutdown in Charge mode or OTG Mode.

This bit is latching. Read this bit to clear the value back to 0.

This bit is not cleared if the fault is still present.

FET_OC

0: No Fault

1: Input OC

FET Overcurrent Shutdown in Charge mode or OTG Mode.

This bit is latching. Read this bit to clear the value back to 0.

This bit is not cleared if the fault is still present

CHG_MODE_INPUT

_OV

0: No Fault

1: Input Over Voltage

VIN OV in Charge Mode

Read to Clear latching Bit.

In Charge Mode, the OV fault time will be set by the delay

time in the VIN_OV_RESTART_DELAY Register. This 40ms

or 100usec delay must expire before a read to clear will

reset this register bit.

CHG_MODE_INPUT

_UV

0: No Fault

1: Charge VIN Under

Voltage

VIN UV in Charge Mode

Read to Clear latching Bit.

ACT2861 Datasheet(PDF) 73 Page - Qorvo, Inc

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