ACT2861 datasheet(45/97 Pages) QORVO

45 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

45 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

QC3.0, etc. This includes USB PD3.0 + PPD. To

achieve this compatibility, the output voltage can be dy-

namically changed in OTG mode. VOUT in OTG mode

can be

dynamically changed by

writing

the

OTG_VOUT[10:0] register, if internal feedback is used

and OTG_VOUT_I2C is set to 0. The OTG_OUT-

PUT_SLEW[1:0] register is used to control the slew rate

between

settings

when

the

OTG_VOUT[10:0]

changed. When the voltage is increased, the internal

ramp and regulator can compensate and increase the

voltage. However, when the voltage is decreased, and

there is no external load on the output, the output volt-

age may not decrease fast enough to the meet the re-

quirements. To speed up the transition time from higher

lower

output

voltages,

set

OTG_PULL-

DOWN_RAMP=1. This turns on an internal 70mA load

when the output voltage is stepped to a lower voltage

using the OTG_VOUT[10:0] register. The 70mA load

turns off when the voltage goes into regulation.

The ACT2861 also has a pulldown current that goes

active

during

any

output

overvoltage

condition.

Enable this feature by setting the I2C bit OTG_PULL-

DOWN_OV = 1.

OTG Mode – State Machine Status

The I2C bits OTG_STATUS[2:0] in register 0x20h pro-

vide the user with real time status of the OTG state ma-

chine. These bits are always 000 when the IC is not in

OTG mode.

Table 10: OTG State Machine Status

OTG_STATUS[2:0]

State Machine State

000

OTG_RST

001

OTG_SS

010

OTG_REG

011

OTG_HICCUP

100

OTG_LL_DIS

101-111

Not Valid

OTG – Battery Temperature Protection

The ACT2861 provides battery temperature in OTG

mode. If the battery temperature goes outside the pro-

grammed range, the IC goes to the OTG_RST state. It

stays there until the temperature returns inside the pro-

grammed range or battery temperature monitoring is

disabled. Note that the OTG thermal limits use the same

registers as the non-JEITA charging registers.

Enable OTG battery temperature monitoring by setting

I2C bit DIS_TH = 0. When this feature is enabled, the IC

compares the battery voltage as measured on the TH

pin to two internal I2C registers: OTG_HOT[1:0] and

OTG_COLD, both in register 0x1Dh.

OTG - Frequency

The ACT2861 OTG switching frequency is the same as

the charging switching frequency. The ACT2861 can

operate at 125kHz, 250kHz, 500kHz, or 1MHz. The

switching frequency is set by the factory and is not user

programmable. The default frequency is 500kHz to give

the best tradeoff between size and efficiency, but can

be programmed to the other options with a custom CMI.

Note that the external component value requirements

change with different switching frequencies. Contact

Qorvo for additional information about other configura-

tions.

OTG – Input Capacitor Selection

Note that the OTG CIN capacitor is also the charging

output capacitor. It is connected directly to VBAT pin.

The capacitor should be dedicated high quality, low-

ESR, ceramic capacitor that is optimally placed to mini-

mize the power routing. 22uF to 47uF capacitors are

typically acceptable, but the final value is application de-

pendent. Choose the input capacitor value to keep the

OTG input voltage ripple less than ~50mV. The COTG in-

put capacitor can be increased without limit.

COTG_IN=IOTG∗VOTGVIN∗�1−VOTGVIN�

FSW∗Vripple Equation6

Where COTG_IN is the OTG input capacitance (Charging

output capacitance) in uF, IOTG is the OTG output cur-

rent in Amperes, VOTG is the OTG output voltage in volts,

VIN is the OTG input voltage in volts, FSW is the switching

frequency in Hz, and Vripple is the maximum allowable

OTG input voltage ripple in volts.

If the OTG input source is a battery, no additional ca-

pacitance is needed. If the OTG input source is a power

supply rail, adding an additional 100 uF bulk electrolytic

capacitor is recommended.

The ceramic capacitor PCB placement is critical. Refer

to the Layout Guidelines selection and to the EVK layout

for details.

Be sure to consider the input capacitor’s DC bias effects.

A capacitor’s actual capacitance is strongly affected by

its DC bias characteristics. The input capacitor is typi-

cally an X5R, X7R, or similar dielectric. Use of Y5U, Z5U,

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