ACT2861 datasheet(47/97 Pages) QORVO

47 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

47 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

ICOMP

RICOMP1

CICOMP1

CICOMP2

Figure 16: OTG Compensation

CHARGE STATUS OUTPUT PIN (NCHG)

The ACT2861 indicates the Charging and OTG states

on the open drain nCHG pin. The nCHG pin typically

drives an LED, but can also be monitored by a micro-

processor GPIO. In Charge mode, the nCHG pin func-

tion is enabled by setting I2C bit DIS_nCHG_CHG in

1. In OTG mode, the nCHG function is enabled by set-

ting the I2C bit EN_OTG_nCHG in register 0x0Fh = 1.

Disable the function by setting it to 0.

Tables 12 and 13 show the nCHG state in different

Charge and OTG operating conditions.

Table 12: nCHG Pin State in Charge Mode

Charging State

nCHG Output Pin

Charging in progress

LOW

Charging complete

HIZ

Charge suspend or Fault

Blinking at 1Hz

Table 13: nCHG Pin State in OTG Mode

OTG State

nCHG Output Pin

OTG Enabled and Output Valid

LOW

OTG Disabled

HIZ

OTG Enabled In Fault, Hiccup, or

Light Load states

HIZ

ADC Monitoring

General Description

The ACT2861 contains a built-in analog to digital con-

verter, ADC, which can be used to monitor seven sys-

tem level parameters. These include input voltage, out-

put voltage, input current, output current, TH pin, die

temperature, and the external ADC input pin. It uses a

single 12 bit delta-sigma ADC that uses an analog input

multiplexer to select one of seven channels for the A/D

conversion. The resulting digital results are stored in

seven digital registers. A seven to one multiplexer con-

nects one of the ADC output registers to the user ac-

cessible register map.

ADC Configuration

The ACT2861 ADC is configured through the I2C inter-

face. It is enabled and disabled by the I2C bit EN_ADC

in register 0x09h. The ADC has two conversion modes,

manual single-shot conversion and automatic polling

conversion.

Single-Shot Conversion

Configure the IC for single-shot conversion mode by

setting the following I2C bits in register 0x09h

ADC_ONE_SHOT = 1.

ADC_CH_SCAN = 0

DIS_ADCBUF = 0

In single shot mode, the user defines the input channel

to be converted and then manually initiates the ADC

conversion. I2C bits ADC_CH_CONV [2:0] in register

0x0Ah select the input channel to be converted.

ADC_CH_READ [2:0] selects the ADC channel to be

read. These should be set to the same channel. The

user initiates an ADC read by writing a 1 into EN_ADC

in register 0x09h. When ADC conversion is complete,

the ADC_DATA_READY bit in register 0x0Ah is set to

1, nIRQ is asserted low, and EN_ADC bit automatically

changes back to 0. The uP can then read the status bits

to find that the ADC conversion is complete. The ADC

data are stored in ADC_OUT [13:6] in register 0x07h

and ADC_OUT[5:2] in register 0x08h. nIRQ stays as-

serted low and the ADC_READY_BIT stays equal to 1

until the ADC data is read. Reading the ADC data auto-

matically deasserts nIRQ. To initiate another ADC con-

version for the same channel, set EN_ADC=1. To initi-

ate an ADC conversion for another channel, change

ADC_CH_CONV and ADC_CH_READ to the appropri-

ate channel and then set EN_ADC=1.

7 to 1

MUX

ADC

CH0

CH1

CH6

CH2

12 Bit

Result

Clock

SEL[2:0]

Figure 17: ADC Block Diagram

ACT2861 Datasheet(PDF) 47 Page - Qorvo, Inc

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