ACT2861 datasheet(30/97 Pages) QORVO

30 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

30 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

30V

20V

10V

20V

VBAT

Buck Mode

Boost Mode

Figure 7: ACT2861 Operating Modes

PFM/PWM Operation

At light loads, the ACT2861 operates in the PFM (pulse

skipping) mode to reduce switching losses in Charge

mode and OTG mode. PFM mode can be disabled by

the I2C bit OTG_DIS_PFM/CHG_DIS_PFM in register

0x10h. Setting this bit to 0 enables PFM mode. Setting

this bit to 1 forces PWM mode. This bit controls both

Charge mode and OTG mode.

Out-of-Audio Mode

When the IC operates in PFM mode, it reduces the

switching frequency. At very light loads, the IC can

switch in the audio range. The ACT2861 features an

Out-of-Audio mode that prevents switching below

31.25kHz. Set the I2C bit AudioFreqLimit = 1 to enable

this feature.

GENERAL DESCRIPTION

Startup

When power is first applied, the ACT2861 always starts

up in SHIP mode. If only a battery is present, the IC re-

mains in SHIP mode until the SHIPM pin is pulled to

ground. The IC then enters HIZ mode where its internal

LDO, VREG, is enabled. In HIZ mode, the IC can com-

municate via I2C.

If power is applied to VIN, the ACT2861 powers up into

SHIP mode and then transitions to HIZ mode when the

voltage goes above 3.9V. At this time, the internal POK,

power ok, signal is released and all registers are reset

to their default values.

Depending on the EN_CHG and nOTG inputs, the IC

then either stays in HIZ mode or moves to the OTG or

CHARGE modes.

VREG LDO

The ACT2861 contains a 100mA internal linear regula-

tor that can be used to power other circuity in the system.

VREG is enabled when the IC enters HIZ mode and the

following two conditions are valid:

VIN is above UVLO (3.9V) or VBAT is above VBATU-

VLO (3.9V)

I2C bit VREG_DIS in register 0x01h = 0. This register bit

can be programmed Hi or Low from the factory to match

system level requirements.

The VREG output voltage is programmable between

2.0V and 5.1V in 100mV steps via I2C bits VREG[4:0] in

VVREG = 2.0V + 0.1V * VREG[4:0].

Where VREG[4:0] is the decimal equivalent of the value

in this register. For example, if VREG[4:0] = 01101b (13

decimal), the output voltage = 2.0V + 0.1V * 13 = 3.3V.

The VREG input can come from either the VIN pin or

the VBAT pin. The ACT2861 contains a Smart Diode

Selector input that minimizes power dissipation by se-

lecting the lower of these two input sources. When the

IC operates in OTG Mode or Charger Mode, the IC pow-

ers VREG from the lower of the VIN or VBAT pins. How-

ever, if the lower voltage pin cannot provide the head-

room needed to regulate VREG, it selects the higher

voltage pin. When the converter is in HIZ mode, VREG

is powered from VIN when possible. If VIN is not present

or is not high enough to support the programmed output

voltage, VREG is powered from VBAT.

The Smart Diode Selector can be overridden and man-

ual control can be selected using the I2C bits

VREG_OVERRIDE and VREG_SELECT in register

0x0Bh. When VREG_OVERRIDE = 0, the Smart Diode

Selector is active. When VREG_OVERRIDE = 1, the

ACT2861 Datasheet(PDF) 30 Page - Qorvo, Inc

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