ACT2861 datasheet(33/97 Pages) QORVO

33 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

33 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

Apply a valid input voltage to the VIN pin for more than

32ms.

Pull the SHIPM pin to ground for greater than 32ms.

IC always transitions to the HIZ MODE before moving

to the CHARGE or OTG modes.

After the IC has exited SHIP MODE, there are three

ways it can be put back into SHIP MODE.

The IC automatically enters Ship mode when

the VIN and VBAT voltages drop below 1V.

Write a 1 into I2C bit SHIPM_ENTER in register

0x00h. After the write command is complete,

the IC stays enabled for 1s to allow the system

to properly power down. After 1s, the IC enters

SHIP MODE and the SHIPM_ENTER bit is re-

set to 0. During the 1s timer count down, the

SHIPM_ENTER bit stays high. Writing a 0 into

SHIPM_ENTER before the 1s timer expires re-

sets the timer and cancels the command.

Pull the SHIPM pin above 4.5V for 32ms. This

function is immediately edge triggered after

32ms, and there no 1s delay.

While in SHIP MODE, the SHIPM pin is pulled up to ap-

proximately 3V with a 1M

Ω pullup resistor. Once IC has

exited SHIP MODE, the SHIPM pin is pulled to GND

with a 1Meg resistor to reduce quiescent current.

If SHIP MODE is not required, connect the SHIPM pin

to GND. With this configuration, when power is applied

to VIN or VBAT, the IC powers up into SHIP MODE for

32ms and then moves into HIZ mode. Note that the

SHIPM pin has a 1.5V logic threshold (1.5V) so it can

be diode OR’ed with a diode to external circuitry like a

Push Button or digital output from an external GPIO.

HIZ Mode

The ACT2861 HIZ mode is a low power state where the

buck-boost converter is disabled. The LDO can be ena-

bled or disabled by I2C bit VREG_EN in register 0x01h.

The IC always starts up in SHIP MODE and then tran-

sitions to HIZ mode before going to either OTG or

Charge mode. If OTG or Charge modes are not enabled,

the IC stays in HIZ state indefinitely. Refer to the Charg-

ing and OTG sections for the details to transition from

HIZ mode to those modes.

To enter HIZ mode from SHIP mode, pull VIN pin high

or pull the SHIPM pin low for > 32ms. The IC enters HIZ

mode from OTG or Charge modes when OTG or charg-

ing are disabled or if a 1 is written into I2C bit HIZ in

Thermal Shutdown

The ACT2861 has thermal shutdown protection that dis-

ables the buck-boost converter when IC junction tem-

perature exceeds TSHUT (160°C). The fault register TSD

is set to 1 and latched when a TSD fault is detected. In

Charge Mode and OTG Mode, the converter restarts

automatically after the junction temperature falls below

TSHUT - TSHUT_HYST, or approximately 160°C - 30°C =

130°C. After the system restarts, the TSD bit is latched

until it is read by I2C.

FET Over Current Protection

The ACT286x closely monitors the HSFETs and

LSFETs currents for safe operation. If any FET exceeds

the maximum cycle-by-cycle current limit threshold set

by I2C bit FET_ILIMIT in register 0x01h, the FET is im-

mediately turned off for that switching cycle. Two

thresholds of 8.5A and 10A are available. If a FET de-

tects the current limit for eight continuous cycles, the

buck-boost converter is latched off. This protection is

valid in both Charger Mode and OTG Mode.

After FET Overcurrent protection is triggered, there are

two ways to clear the fault to let the converter resume

normal

operation.

First

set

I2C

bit

DIS_OCP_SHUTDOWN = 1 in register 0x01h. It can

also be cleared by putting the IC into HIZ mode. In OTG

mode, toggle the nOTG pin to put the IC into HIZ mode

and then restart OTG mode. In Charge mode, toggle the

EN_CHG pin.

Overcurrent protection can be disabled by setting the

I2C bit DIS_OCP_SHUTDOWN = 1.

Watchdog Timer

The ACT2861 contains a watchdog timer to detect sys-

tem level communication failures. The watchdog timer

requires the host to periodically write a 1 into I2C bit

WATCHDOG_RESET in register 0x00h. If the host

latches up or is unable to perform the write command

before the watchdog timer times out, the IC enters

FAULT mode and disables the switching converter. The

timer resets after each write to WATCHDOG_RESET.

WATCHDOG_RESET is an auto-clearing register. It au-

tomatically resets back to 0 after it is set to 1.

The timeout value is controlled by I2C bit WATCH-

DOG[1:0] in register 0x01h. It can be set between 80s

and 320s. If the IC is used in stand-alone operation, the

watchdog timer can be disabled by setting WATCH-

DOG[1:0] = 00.

WATCHDOG is always disabled in HIZ Mode and can-

not be enabled in HIZ. In addition, the timer is reset to 0

when entering HIZ mode and automatically starts count-

ing when exiting HIZ mode into OTG or Charge Mode.

ACT2861 Datasheet(PDF) 33 Page - Qorvo, Inc

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