ACT2861 datasheet(31/97 Pages) QORVO

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Data Sheet Rev. F, April 2022 | Subject to change without notice

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

VREG input is determined by VREG_SELECT. When

VREG_SELECT = 0, the input is VIN. When VREG_SE-

LECT = 1, the input is VBAT.

If VREG LDO is overloaded or not within spec, the buck-

boost

converter

shuts

down,

and

I2C

fault

bit

VREG_OC_UVLO in register 0x05h is set to 1.

Additionally, if VREG is held in current limit for more

than 90us, it shuts down for 100ms to prevent damage.

It tries to restart after 100ms. It continues this cycle until

the current limit condition is removed. VREG also con-

tains UVLO detection, which is set to 88% of the pro-

grammed output voltage.

If the VREG output is in current limit for 90usec, or the

VREG voltage is below the UVLO threshold while the IC

is in Charge mode, the charger state machine moves to

the FAULT state and stops charging. If in OTG mode,

the OTG state machine moves to the OTG_RST state.

In both cases, the buck-boost converter stops switching.

VREG can be programmed to ignore an overvoltage or

undervoltage fault with I2C bits DIS_CHG_VREG_FLT

in register 0x0Dh and DIS_OTG_VREG_FLT in register

0x10h. If these bits are set to 1, Charge or OTG mode

continue to operate through the fault condition.

VREG requires a high quality, low-ESR, ceramic output

capacitor. A 1uF is typically suitable, but this value can

be increased without limit. The output capacitor should

be a X5R, X7R, or similar dielectric. The effective output

capacitance must be greater than 0.7uF to ensure LDO

stability.

VREG contains a fixed 250us soft-start to reduce inrush

current.

Interrupt Output Pin (nIRQ)

The nIRQ output pin can be used to signal a fault or

other system effects. The conditions below can assert

the nIRQ pin. All fault conditions can be individually

masked using the I2C nIRQ Control Registers 0x1Eh,

0x1Fh, and 0x20h. To clear the interrupt and de-assert

the nIRQ pin, write a 1 into I2C bit nIRQ_CLEAR in reg-

ister 0x05h. nIRQ_CLEAR is a self-clearing register bit.

nIRQ_CLEAR always returns a 0 when read, even after

it is set to 1.

General nIRQ Fault Conditions

Watchdog Expired - If the watchdog timer ex-

pires at any time, it asserts nIRQ. This is a level

sensitive function. The watchdog timer must be

reset or disabled and a 1 must be written into

nIRQ_CLEAR to de-asserted nIRQ.

VREG LDO Overcurrent or Under-voltage

Lockout - Any time the VREG LDO is in over-

current or under-voltage lockout, nIRQ is as-

serted. This is a level sensitive function. VREG

must be in regulation AND a 1 must be written

into nIRQ_CLEAR to deassert nIRQ. If the

VREG LDO is in the 100ms shutdown wait pe-

riod, it will not clear the nIRQ output. This fault

is detected in HIZ mode, Charge Mode, and

OTG Mode.

Battery voltage is lower than VBAT_GOOD – Any

time the VBAT pin voltage falls below the

VBAT_GOOD threshold, nIRQ is asserted. This is

an edge triggered function after a 16ms deglitch.

Write 1 to into nIRQ_CLEAR to deassert nIRQ.

VBAT_GOOD is not checked in HIZ mode, so nIRQ

is not triggered in HIZ mode. If VBAT is lower

than VBAT_GOOD in HIZ mode, nIRQ is not trig-

gered, but it is immediately triggered when the

IC moves into the Charge or OTG modes.

Over Temperature Shut Down - Any time the

die temperature exceeds the TSHUT (160°C)

threshold, nIRQ is asserted. This is a level sen-

sitive function. The die temperature must be be-

low the TSHUT_HYST AND a 1 must be written into

nIRQ_CLEAR to deassert nIRQ. Die TSD is

active in all modes.

FET Overcurrent Fault – If the IC is disabled

from switching because of a FET overcurrent

fault, nIRQ is asserted. This is a level sensitive

function. This fault is latched, so the latch must

cleared by manually going into HIZ Mode AND

a 1 must be written into nIRQ_CLEAR to deas-

sert nIRQ. This fault can only be triggered in

CHG or OTG mode.

ADC Data Ready – If the ADC is enabled, and

a conversion is completed, nIRQ is asserted.

This is an edge triggered event. A 1 must be

written into nIRQ_CLEAR to deassert nIRQ.

This is active in all modes when the ADC is en-

abled.

HIZ Enter – The ACT2861 asserts nIRQ when

it enters HIZ mode. This is an edge triggered

event. 1 must be written into nIRQ_CLEAR to

deassert nIRQ. The IC asserts nIRQ when en-

tering HIZ mode to signal a fault or other condi-

tion that might have caused the IC to jump out

of charge mode or OTG mode un-expectantly.

I2C Fault – If an I2C command takes more than

100ms between the start bit and the stop bit,

nIRQ is asserted. This is an edge triggered

event. The I2C state machine clears out any

partial data, resets, and waits for another start

bit for another I2C command. The state ma-

chine clears and restarts the 100ms timer when

it receives the next start bit.

ACT2861 Datasheet(PDF) 31 Page - Qorvo, Inc

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