ACT2861 datasheet(50/97 Pages) QORVO

50 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

50 of 97

www.qorvo.com

ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

PC board layout guidance

Proper parts placement and PCB layout are critical to

the operation of switching power supplies. Follow the

following

layout

guidelines

when

designing

the

ACT2861 PCB. Refer to the Qorvo ACT2861 Evaluation

Kit for layout guidance.

Place the ceramic input and output capacitors

as close as possible to the IC. Connect the in-

put capacitors directly between VIN and PGND

pins on the top layer. Connect the output capac-

itors directly between VBAT and PGND pins on

the top layer. Use 1206 sized capacitors to al-

low for proper switch pin routing. Note that the

input and output capacitor placement is critical.

Qorvo strongly recommends following the EVK

input capacitor and output capacitor placement

and routing. The bulk input and output capacitor

placement is not as critical. Bulk capacitors

should be placed on the opposite side of the

sense resistors from the ceramic capacitors.

Minimize the switch node trace lengths be-

tween the SW1 and SW2 pins and the inductor.

Optimal switch node routing is to run the traces

between the input and output capacitors’ pads.

Using 1206 or larger sized capacitors is recom-

mended. Avoid routing sensitive analog signals

near these high frequency, high dV/dt traces.

Qorvo strongly recommends following the EVK

inductor placement and PCB routing.

The VBATS pin should be Kelvin connected to

the battery. Keep this trace away from the SW1

and SW2 traces to prevent noise injection. The

IC regulates the battery voltage to this Kelvin

connection.

The PGND and AGND ground pins must be

electrically connected together. The AGND

ground plane should be isolated from the rest

of the PCB power ground. These two ground

pins should be connected together right at the

IC.

Connect the exposed pad directly to the top

layer PGND pins and ground plane. Connect

the top layer ground plane to both internal

ground planes and the PCB backside ground

plane with thermal vias. Provide ground plane

routing on multiple layers to allow the IC’s heat

to flow into the PCB and then spread radially

from the IC. Avoid cutting the ground planes or

adding vias that restrict the radial flow of heat.

Make Kelvin connections to the ILIM and OLIM

current sense resistors. Route the current

sense signals close to each other and keep

them away from noisy switching signals.

The current sense filter capacitors and induc-

tors should be placed directly by their respec-

tive ISRP, ISRN, OSRP, and OSRN pins.

Remember that all open drain outputs need

pull-up resistors.

The following components should be con-

nected to the AGND plane.

ILIM resistor

OLIM resistor

COMP resistor and capacitors

VREG bypass capacitor

INTBP bypass capacitor

10. The ACT2861 footprint must connect the VIN

pins 23, 24, and 35 on the top layer. It must con-

nect the SW1 pins 21, 22, and 34 on the top

layer. It must connect the SW2 pins 18, 19, and

33 on the top layer.

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