ACT2861 datasheet(25/97 Pages) QORVO

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Data Sheet Rev. F, April 2022 | Subject to change without notice

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

When in the FAULT state, the nCHG pin blinks at a 1HZ

rate to indicate a fault condition.

OTG STATE MACHINE

The ACT2861 has a dedicated OTG state machine.

This state machine handles the startup, normal opera-

tion and fault conditions in OTG mode.

OTG Reset State (OTG_RST)

The OTG state machine always starts from the

OTG_RST state. All OTG operation starts from this

state. In this state, the switcher is disabled and the state

machine is waiting for all the required conditions to

move to the OTG_SS state.

After all the following fault conditions are cleared, the IC

starts the OTG Enable Delay Timer. This timer is con-

trolled by I2C bit OTG_EN_DLY[1:0] in register 0x0Fh.

Once the timer has expired, the state machine moves

to the OTG_SS state.

OTG Reset Faults:

OTG_VBAT_CUTOFF voltage: This fault is active

when the battery voltage is lower than the programmed

OTG battery cutoff voltage. The cutoff voltage is set by

I2C bit OTG_VBAT_CUTOFF in register 0x0Fh. This

fault self-clears when VBAT is higher than the OTG bat-

tery cutoff voltage.

VREG LDO OK – This fault is set when an LDO fault is

detected. This includes the 100msec timeout period.

This fault automatically clears when the VREG LDO has

exited the faulted condition. Note: This fault can be

masked to allow the state machine to exit OTG_RST

while there is a fault on the VREG LDO by using the I2C

bit DIS_OTG_VREG_FLT in register 0x10 Bit 1.

OTG HOT or OTG COLD: This fault is active if the bat-

tery temperature as detected on the TH pin is above or

below the programmed temperature thresholds. This

fault self-clears when the battery temperature goes

back into the allowable range.

Watchdog Timer Fault: This fault is active if the watch-

dog timer is enabled and the timer times out. This fault

clears when the watchdog timer is reset or cleared. It

can be reset by writing a 1 into the I2C bit WATCH-

DOG_RESET in register 0x00h. It can be cleared by

disabling the watchdog timer by setting I2C bits

WATCHDOG[1:0] = 0x00h.

During this state, the Fast Charge Safety and Low Bat-

tery Safety Timer timers are suspended and held at their

current value.

FET Overcurrent Fault: This fault is set if a switching

FET exceeds the cycle-by-cycle current limit for 8 (or 16)

consecutive cycles. The FET_OC fault is latched. To

clear this latch, the IC must exit the OTG mode and en-

ter HIZ mode. This is typically accomplished by toggling

the nOTG pin or setting the HIZ register to 1.

VBAT Overvoltage: This fault is set if VBAT exceeds

the VOTG_BAT_OV voltage. The OV fault self-clears when

VBAT drops below VOTG_BAT_OV and the IC exits the

OTG_RST state.

Die Thermal Shutdown (TSD): This fault is active

when die temperature exceeds the TSHUT (160°C) tem-

perature. This fault self-clears when the die temperature

cools down by the temperature hysteresis, TSHUT_HYST

(30°C). This fault cannot be cleared or masked. The IC

must cool down before exiting the OST_RST state.

OTG Softstart State (OTG_SS)

In this state, the IC enables the converter and softstarts

the OTG output voltage.

The state machine enters OTG_SS from the OTG_RST

state when all faults are cleared. The state machine

transitions to the OTG_REG state after the OTG output

is softstarted an in regulation.

The softstart time is controllable by the I2C bit OTG_SS

in register 0x0Eh. If a fault occurs during the softstart,

the state machine jumps back to the OTG_RST state

and disables the converter. Once the soft start is done,

the IC jumps to the OTG_REG state.

OTG Regulation State (OTG_REG)

The normal regulation occurs in the OTG_REG state.

If a major fault occurs during operation the IC will jump

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