ACT2861 datasheet(42/97 Pages) QORVO

42 / 97 page

Data Sheet Rev. F, April 2022 | Subject to change without notice

42 of 97

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ACT2861

30V Buck-Boost Charger with Integrated MOSFETs and OTG

The bulk capacitor should be placed on the left side of

the current sense resistor.

Charger – Output Capacitor Selection

Note that the Charger COUT capacitor is also the OTG

input capacitor. It is connected directly to VBAT pin. The

capacitor should be dedicated high quality, low-ESR,

ceramic capacitor that is optimally placed to minimize

the power routing. 22uF to 47uF capacitors are typically

acceptable, but the final value is application dependent.

Choose the output capacitor value to keep the charger

output voltage ripple less than ~50-100mV. The output

capacitor can be increased without limit.

CCHG_OUT=ICHG∗VBATVIN∗�1−V��VIN�

FSW∗Vripple

Where CCHG_OUT is the charging output capacitance in

uF, ICHG is the charging current in Amperes, VBAT is the

battery voltage in volts, VIN is the input voltage in volts,

FSW is the switching frequency in Hz, and Vripple is the

maximum output voltage ripple in volts.

The ceramic capacitor PCB placement is critical. Refer

to the Layout Guidelines selection and to the EVK layout

for details.

Be sure to consider the input capacitor’s DC bias effects.

A capacitor’s actual capacitance is strongly affected by

its DC bias characteristics. The output capacitor is typi-

cally an X5R, X7R, or similar dielectric. Use of Y5U, Z5U,

or similar dielectrics is not recommended. Output ca-

pacitor placement is critical for proper operation. The

output capacitor must be placed as close to the IC as

possible. The traces from VBAT to the capacitor and

from the capacitor to PGND should as short and wide

as possible.

The bulk capacitor should be placed on the right side of

the current sense resistor.

OTG MODE

The ACT2861 supports on-the-go, OTG, mode buck-

boost converter operation. In this mode, the IC delivers

power from the battery to power other portable devices.

OTG Enable / Disable

The ACT2861 can only enter OTG mode from HIZ mode.

Note that if the IC is commanded to enter both OTG

mode and Charge mode at the same time, OTG mode

takes precedence. When in HIZ mode, OTG mode can

be enabled by the nOTG pin or I2C. In either case, the

I2C bit EN_OTG in register 0x0Eh must be = 1 to enable

OTG mode. Then pull the nOTG pin low to enter OTG

mode.

OTG Mode can also be enabled with the I2C bits

OTG_EN and OTG_EN_OVERRIDE in register 0x0Eh.

Setting OTG_EN = 1 enables OTG mode. Then set

OTG_EN_OVERRIDE = 1 to enter OTG mode. Note

that the OTG_EN_OVERRIDE bit overrides the nOTG

pin. Figure 14 shows both the hardware and I2C condi-

tions required to enter OTG mode.

Note that in all cases, the I2C bit HIZ in register 0x00h

must be = 0 to enter OTG mode. When HIZ = 1, the IC

is forced into HIZ mode and both OTG mode and

Charge mode are disabled.

HIZ bit = 0

OTG_EN bit = 1

nOTG pin = 0

OTG_EN_OVERRIDE bit = 1

HIZ to

OTG

Mode

Figure 14: Conditions to Enter OTG Mode from HIZ

Mode

After the IC is in OTG mode, the conditions to exit OTG

mode change. When OTG mode is disabled, the IC

state machine must go to HIZ mode or to SHIP mode.

There are several ways to disable OTG mode and go to

HIZ mode.

Set the I2C HIZ bit = 1

Set the I2C OTG_EN bit = 0

Pull the nOTG pin high and set the I2C

OTG_EN_OVERRIDE bit = 0.

The IC also exits OTG mode if there is an OTG

overvoltage condition for longer than 100ms.

OTG mode can also be disabled by putting the IC into

SHIP mode.

HIZ bit = 1

OTG_EN bit = 0

nOTG pin = 1

OTG_EN_OVERRIDE bit = 0

OTG to

HIZ

Mode

OTG_VOUT_OV bit = 1

100ms deglitch

Figure 15: Conditions to Enter HIZ Mode from OTG

Mode

OTG Output Voltage Setting

The OTG output voltage is programmable between

2.96V and 23.42V in 20mV steps via by I2C bits

OTG_VOUT[9:0] in registers 0x13h and 0x14h.

��=2.96��+20��∗��_��[9:0]

ACT2861 Datasheet(PDF) 42 Page - Qorvo, Inc

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