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IMX93CEC Datasheet(PDF) 23 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 123 page ![]() Table 21. The power supply states ...continued Power rail OFF BBSM SUSPEND (Analog on) IDLE RUN/LP RUN VDD_ANA_0P8 VDD_MIPI_0P8 VDD_USB_0P8 OFF OFF ON ON ON VDD_ANAx_1P8 VDD_LVDS_1P8 VDD_MIPI_1P8 VDD_USB_1P8 VDD_USB_3P3 OFF OFF ON ON ON 4.2.2 Low power modes The state of each module in the IDLE, SUSPEND, and BBSM mode are defined in the Table 22. Table 22. Low power mode definition IDLE SUSPEND BBSM CCM LPM mode WAIT STOP N/A Arm Cortex®-A55 CPU0 OFF OFF OFF Arm Cortex®-A55 CPU1 OFF OFF OFF Shared L3 cache ON OFF OFF Display OFF OFF OFF DRAM controller and PHY ON OFF OFF ARM_PLL OFF OFF OFF DRAM_PLL OFF OFF OFF SYSTEM_PLL 1/2/3 ON OFF OFF XTAL ON OFF OFF RTC ON ON ON External DRAM device Self-Refresh Self-Refresh OFF USB PHY In Low Power State OFF OFF DRAM clock 266 MHz OFF OFF Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 23 / 123 |
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