IMX93CEC datasheet(55/123 Pages) NXP

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SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD1

SD8

SD2

SD3

SD4/SD5

SD6

SD7

Figure 26. SDR50/SDR104 timing

Table 59. SDR50/SDR104 interface timing specification (Nominal and Overdrive mode)[1],[2]

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

—

SD2

Clock Low Time

tCL

2.2

—

SD3

Clock High Time

tCH

2.2

—

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4

uSDHC Output Delay

tOD

-3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.4

—

SD7

uSDHC Input Hold Time

tIH

1.5

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)[3]

SD8

uSDHC Input Data Window

tODW

0.5 x tCLK

—

[1] Input timing assumes an input signal slew rate of 1 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm, unterminated, 2-inch microstrip trace

on standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance of the transmission line should be matched closely to the RDSON of the I/O pad

output driver.

[3] Data window in SDR100 mode is variable.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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