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IMX93CEC Datasheet(PDF) 31 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 31 Page - NXP Semiconductors |
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31 / 123 page ![]() Table 28. General purpose I/O (GPIO) AC parameters...continued Symbol Description Min Typ Max Unit Condition (1.62 V, 1.8 V, 1.98 V), Drive strength X6 tF TX fall time 349 — 506 ps Slew rate FSEL1 = 11b, Fast Slew Rate (1.62 V, 1.8 V, 1.98 V), Drive strength X6 tR TX rise time 4030 — 5790 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X1 tF TX fall time 4410 — 6290 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X1 tR TX rise time 1870 — 2950 ps Slew rate FSEL1 = 11b, Fast Slew Rate (1.62 V, 1.8 V, 1.98 V), Drive strength X2 tF TX fall time 1900 — 3310 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X2 tR TX rise time 774 — 1930 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X3 tF TX fall time 719 — 2070 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X3 tR TX rise time 598 — 1360 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X4 tF TX fall time 490 — 1590 ps Slew rate FSEL1 = 11b, Fast Slew Rate (3 V, 3.3 V, 3.465 V), Drive strength X4 4.6.2 DDR I/O AC electrical characteristics The DDR I/O pads support LPDDR4/LPDDR4X operational modes. The DDRC is compliant with JEDEC-compliant SDRAMs. DDRC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the hardware development guide for the i.MX 93 application processor. NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 31 / 123 |
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