IMX93CEC datasheet(35/123 Pages) NXP

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Table 32. JTAG Timing[1],[2]

Parameter

All Frequencies

Unit

Min

Max

SJ0

JTAG_TCK frequency of operation[3],[4]

—

MHz

SJ1

JTAG_TCK cycle time in crystal mode

—

SJ2

JTAG_TCK clock pulse width measured at VM[5]

—

SJ3

JTAG_TCK rise and fall times

—

SJ4

Boundary scan input data set-up time

—

SJ5

Boundary scan input data hold time

—

SJ6

JTAG_TCK low to output data valid

—

600

SJ7

JTAG_TCK low to output high impedance

—

600

SJ8

JTAG_TMS, JTAG_TDI data set-up time

—

SJ9

JTAG_TMS, JTAG_TDI data hold time

—

SJ10

JTAG_TCK low to JTAG_TDO data valid

—

SJ11

JTAG_TCK low to JTAG_TDO high impedance

—

SJ14

JTAG_TCK low to JTAG_TDO data invalid

—

[1] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 Ω, unterminated, 5-inch microstrip trace on

standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance of the transmission line can be equal to the selected RDSON

of the I/O pad output driver.

[3] TDC = target frequency of JTAG

[4] 50 MHz frequency is for the JTAG debug interface. For boundary scan, the maximum TCK frequency is 10 MHz.

[5] VM = mid-point voltage

4.8.4 SWD timing parameters

The DSE[5:0] = 001111 and FSEL1[1:0] = 11 are required drive settings to meet the timing.

Figure 13 depicts the SWD timing.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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