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Table 48. SPDIF timing parameters ...continued

Parameter

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_SR_CLK low period

srckpl

16.0

—

Modulating Tx clock (SPDIF_ST_CLK) period

stclkp

40.0

—

SPDIF_ST_CLK high period

stclkph

16.0

—

SPDIF_ST_CLK low period

stclkpl

16.0

—

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

Figure 17. SPDIF_SR_CLK timing diagram

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

Figure 18. SPDIF_ST_CLK timing diagram

4.10.3 PDM Microphone interface timing parameters

Note: These timing requirements apply only if the clock divider is enabled (PDM_CTRL2[CLKDIV] = 0), otherwise there are no

special timing requirements.

The PDM microphones must meet the setup and hold timing requirements shown in the following table. The "k" factor value in

Table 49 depends on the selected quality mode as shown in Table 50.

Table 49. PDM timing parameters

Parameter

Value

trs, tfs

@ (moduleNickname)_CLK_ROOTrate

floor (kxCLKDIV) - 1

[1]

trh, tfh

≥ 0

[1] Depending on K value, user must make sure floor (K x CLKDIV) > 1 to avoid timing problems.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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