IMX93CEC datasheet(62/123 Pages) NXP

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RMII_REF_CLK

ENET_TX_EN

M16

M17

M18

M19

M20 M21

ENET_RD[1:0]

ENET_TD[1:0]

ENET_RX_ER

ENET_CRS_DV

Figure 31. RMII mode signal timing diagram

Table 66. RMII signal timing[1],[2],[3]

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

RMII_REF_CLK

period

M17

RMII_REF_CLK pulse width low

35%

65%

RMII_REF_CLK

period

M18

RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid

—

M19

RMII_REF_CLK to ENET0_TXD[1:0], ENET_TX_EN valid

—

M20

ENET_RX_DATA[1:0], ENET_CRS_DV, ENET_RX_ER to

RMII_REF_CLK setup

—

M21

RMII_REF_CLK to ENET_RX_DATA[1:0], ENET_CRS_DV,

ENET_RX_ER hold

—

[1] The timings assume the following configuration: DSE[5:0] = 001111 and FSEL1[1:0] = 11.

[2] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[3] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm, unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

4.12.3.3 MII serial management channel timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification.

Figure 32 shows MII asynchronous input timings. Table 67 describes the timing parameters (M10–M15) shown in the figure.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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