IMX93CEC datasheet(65/123 Pages) NXP

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Table 69. LPSPI Controller mode timing[1],[2]

Number

Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of LPSPI clock[3]

—

MHz

[4]

—

MHz

[5]

tSCK

SCK period

2 x tperiph

—

[6]

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

tSCK / 2 + 3

—

tSU

Data setup time (inputs)

—

[7],[8]

tHI

Data hold time (inputs)

—

[7]

Data valid (after SCK edge)

—

2.5

—

tHO

Data hold time (outputs)

-2.5

—

[1] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm. Unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

[3] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

[4] The clock driver in the LPSPI module for fperiph must guaranteed this limit is not exceeded.

[5] In Controller loopback mode when LPSPI_CFGR1[SAMPLE] bit is 1.

[6] fperiph = Functional clock / (2 ^ PRESCALE) and tperiph = 1 / fperiph

[7] If LPSPI_CFGR1[SAMPLE] bit is 1, the data setup time (inputs) / data hold time (inputs) specifications are same with the one in Peripheral mode.

[8] For 3.3 V I/O supply, tSU (Data setup time) parameter value is 9 ns in LPSPI Controller mode.

(OUTPUT)

MSB IN2

LSB IN

MSB OUT2

LSB OUT

(CPOL=0)

SCK

(CPOL=1)

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

PCS1

(OUTPUT)

SOUT

(OUTPUT)

SIN

(INPUT)

BIT 6 . . . 1

tLead

tSCK

tLag

tW SCK

tSU

tHI

tHO

tRI/FI

tRO/FO

Figure 35. LPSPI Controller mode timing (CPHA = 0)

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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