Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

IMX93CEC Datasheet(PDF) 61 Page - NXP Semiconductors

Part # IMX93CEC
Description  i.MX 93 Applications Processors Data Sheet for Commercial Products
PDF  123 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX93CEC Datasheet(HTML) 61 Page - NXP Semiconductors

Back Button IMX93CEC Datasheet HTML 57Page - NXP Semiconductors IMX93CEC Datasheet HTML 58Page - NXP Semiconductors IMX93CEC Datasheet HTML 59Page - NXP Semiconductors IMX93CEC Datasheet HTML 60Page - NXP Semiconductors IMX93CEC Datasheet HTML 61Page - NXP Semiconductors IMX93CEC Datasheet HTML 62Page - NXP Semiconductors IMX93CEC Datasheet HTML 63Page - NXP Semiconductors IMX93CEC Datasheet HTML 64Page - NXP Semiconductors IMX93CEC Datasheet HTML 65Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 61 / 123 page
background image
• 802.1Qbu Frame preemption
• Time based Scheduling
• 1.8 V/3.3 V RMII operation, 1.8 V RGMII operation
4.12.3.1 Ethernet QOS signal mapping
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints
for the physical interface.
Table 65. ENET QOS signal mapping[1]
Pad name
RGMII
Alt mode
RMII
Alt mode
Direction
ENET1_MDC
RGMII_MDC
Alt 0
RMII_MDC
Alt 0
O
ENET1_MDIO
RGMII_MDIO
Alt 0
RMII_MDIO
Alt 0
I/O
ENET1_TXC
RGMII_TXC
Alt 0
RMII_TX_ER
Alt 1
O
ENET1_TX_CTL
RGMII_TX_CTL
Alt 0
RMII_TX_EN
Alt 0
O
ENET1_TD0
RGMII_TD0
Alt 0
RMII_TD0
Alt 0
O
ENET1_TD1
RGMII_TD1
Alt 0
RMII_TD1
Alt 0
O
ENET1_TD2
RGMII_TD2
Alt 0
RMII_REF_CLK[2]
Alt 1
I/O
ENET1_TD3
RGMII_TD3
Alt 0
—
Alt 0
O
ENET1_RXC
RGMII_RXC
Alt 0
RMII_RX_ER
Alt 1
I
ENET1_RX_CTL
RGMII_RX_CTL
Alt 0
RMII_CRS_DV
Alt 0
I
ENET1_RD0
RGMII_RD0
Alt 0
RMII_RD0
Alt 0
I
ENET1_RD1
RGMII_RD1
Alt 0
RMII_RD1
Alt 0
I
ENET1_RD2
RGMII_RD2
Alt 0
—
Alt 0
I
ENET1_RD3
RGMII_RD3
Alt 0
—
Alt 0
I
[1] ENET1 is Ethernet QoS with TSN, while ENET2 is Ethernet MAC.
[2] The signal can be either input or output.
4.12.3.2 RMII mode timing
In RMII mode, enet1.RMII_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock.
Figure 31 shows RMII mode timings. Table 66 describes the timing parameters (M16–M21) shown in the figure.
NXP Semiconductors
IMX93CEC
i.MX 93 Applications Processors Data Sheet for Commercial Products
IMX93CEC
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 7 — 12 February 2026
Document feedback
61 / 123



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com