IMX93CEC datasheet(79/123 Pages) NXP

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4.12.12.1 Pad/Package/Board connections

The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link.

Each USBx_VBUS pin must be isolated by an external 30 KΩ 1% precision resistor.

The USB 2.0 PHY uses USBx_TXRTUNE and an external resistor to calibrate the USBx_DP/DN 45 Ω source impedance. The

external resistor value is 200 Ω 1% precision on each of USBx_TXRTUNE pad to ground.

5 Boot mode configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation.

i.MX 93 supports three different boot modes:

• Normal Boot Mode

• Boot from Internal Fuse Mode

• Serial Download Boot Mode

Three different boot modes can be either selected via different boot mode pins or overridden by fuses.

i.MX 93 has two kinds of boot type:

• Single Boot: Cortex®-A55 core is in charge of loading all containers and images, while Cortex®-M33 core is doing nothing

except waiting Cortex®-M33 firmware is loaded and available during boot.

• Low Power Boot (LPB): only Cortex®-M33 core is running after POR. Cortex®-A55 core cannot be triggered by Cortex®-

M33 firmware.

For detailed boot mode configuration, see the "Fuse Map" and the "System Boot" chapter in

i.MX 93 Reference

Manual (IMX93RM).

5.1 Boot mode configuration pins

There are four boot mode pins used to select boot mode.

Table 93. Fuses and associated pins used for boot

BOOT_MODE[3:0]

Function

x000

Boot from Internal Fuses

0001

Serial Download (USB1)

0010

uSDHC1 8-bit eMMC 5.1

0011

uSDHC2 4-bit SD 3.0

0100

FlexSPI Serial NOR

0101

FlexSPI Serial NAND 2K

0110

Reserved

0111

Reserved

1000

LPB: Boot from Internal Fuses

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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