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IMX93CEC Datasheet(PDF) 88 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 88 Page - NXP Semiconductors |
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88 / 123 page  Table 102. 11 x 11 mm functional contact assignment ...continued Ball name 11 x 11 ball Power group Ball Types Default setting Default modes Default function Status while reset is asserted DRAM_DQ15_A P1 VDDQ_DDR DDR — — — DRAM_DQS0_C_A L4 VDDQ_DDR — — — — DRAM_DQS0_T_A N4 VDDQ_DDR DDRCLK — — — DRAM_DQS1_C_A R5 VDDQ_DDR — — — — DRAM_DQS1_T_A R4 VDDQ_DDR DDRCLK — — — DRAM_MTEST1 D4 VDDQ_DDR DDR — — — DRAM_RESET_N D2 VDDQ_DDR DDR — — — DRAM_ZQ E4 VDDQ_DDR DDR — — — ENET1_MDC AA11 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[0] Input with PD ENET1_MDIO AA10 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[1] Input with PD ENET1_RD0 AA8 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[10] Input with PD ENET1_RD1 Y9 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[11] Input with PD ENET1_RD2 AA9 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[12] Input with PD ENET1_RD3 Y10 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[13] Input with PD ENET1_RX_CTL Y8 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[8] Input with PD ENET1_RXC AA7 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[9] Input with PD ENET1_TD0 W11 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[5] Input with PD ENET1_TD1 T12 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[4] Input with PD ENET1_TD2 U12 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[3] Input with PD ENET1_TD3 V12 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[2] Input with PD ENET1_TX_CTL V10 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[6] Input with PD ENET1_TXC U10 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[7] Input with PD ENET2_MDC Y7 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[14] Input with PD Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 88 / 123 |
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