IMX93CEC datasheet(53/123 Pages) NXP

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Table 56. HS400 interface timing specification (Low drive mode)[1],[2] ...continued

Parameter

Symbols

Min

Max

Unit

SD2

Clock low time

tCL

3.3

—

SD3

Clock high time

tCH

3.3

—

uSDHC Output/Card Inputs DAT (Reference to SCK)

SD4

Output skew from data of edge of SCK

tOSkew1

0.45

—

SD5

Output skew from edge of SCk to data

tOSkew2

0.45

—

uSDHC Input/Card Outputs DAT (Reference to Strobe)

SD6

uSDHC input skew

tRQ

—

0.45

SD7

uSDHC hold skew

tRQH

—

0.45

[1] Input timing assumes an input signal slew rate of 1 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm, unterminated, 2-inch microstrip trace

on standard FR4 (3.3 pF/inch). For best signal integrity, the series resistance of the transmission line should be matched closely to the RDSON of the I/O pad

output driver.

4.12.1.4 HS200 Mode AC timing

Figure 25 depicts the timing of HS200 mode, Table 57 and Table 58 list the HS200 timing characteristics.

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD5

SD2

SD3

SD1

Figure 25. HS200 timing

Table 57. HS200 interface timing specification (Nominal and Overdrive mode)[1],[2]

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

2.2

—

SD3

Clock High Time

tCH

2.2

—

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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