IMX93CEC datasheet(77/123 Pages) NXP

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[1] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

[2] The actual maximum frequency supported is limited by the FlexSPI

n_MCR0[RXCLKSRC] configuration used, see the FlexSPI SDR input timing specifications.

[3] TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register. See i.MX 93 Applications Processor Reference Manual (IMX93RM) for more details.

TCSS

TCK

TCSH

T DVO

T DHO

TDVO

TDHO

FLEXSPI_SCLK

FLEXSPI_SSx_B

FLEXSPI_DATA[7:0]

Figure 48. FlexSPI output timing in SDR mode

4.12.9.2.2 DDR mode

Table 90. FlexSPI output timing in DDR mode (Nominal and Overdrive mode)[1]

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[2]

—

200

MHz

Tck

SCK clock period

—

TDVO

Output data valid time

—

1.815

TDHO

Output data hold time

0.615

—

TCSS

Chip select output setup time

(TCSS + 0.5) x

Tck - 0.6

—

TCSH

Chip select output hold time

[3]

(TCSH + 0.5) x

Tck - 0.6

—

[1] These timing specifications are valid only for 1.8 V nominal IO pad supply voltage. see Table 91

[2] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

[3] TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register. See i.MX 93 Applications Processor Reference Manual (IMX93RM) for more details.

Table 91. FlexSPI output timing in DDR mode (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[1]

—

133[2]

MHz

Tck

SCK clock period

7.5

—

TDVO

Output data valid time

—

2.75

TDHO

Output data hold time

0.9

—

TCSS

Chip select output setup time[3]

(TCSS + 0.5) x

Tck - 0.9

—

Table continues on the next page...

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

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Product data sheet

Rev. 7 — 12 February 2026

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