IMX93CEC datasheet(25/123 Pages) NXP

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Table 23. Chip power in different LP modes ...continued

Mode

Supply

Voltage (V)

Power (mW)[1]

VDD_ANA*_1P8

1.8

1.85

VDD_ANA_0P8

0.8

0.40

VDD_MIPI_0P8

0.8

0.65

VDD_USB_0P8

0.8

0.45

VDD_USB_3P3

3.3

0.25

VDD_SOC

0.65

7.40

Total[3]

—

15.1

[1] All the power numbers defined in the table are at 25oC. Use case dependent.

[2] To achieve this low power consumption values for I/O power rails in SUSPEND mode, it is recommended to configure the IOMUX of those pins to GPIO input and

change the PAD control settings to pull-up or pull-down depends on the board design before entering SUSPEND mode.

[3] Sum of the listed supply rails.

4.3 Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this

section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the processor (worst-case scenario)

Figure 4 illustrates an example about power sequence of i.MX 93 processors.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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