IMX93CEC datasheet(51/123 Pages) NXP

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4.12.1.2 SD3.0/eMMC5.1 (dual data rate) AC timing

Figure 23 depicts the timing of SD3.0/eMMC5.1 (DDR). Table 54 lists the SD3.0/eMMC5.1 (DDR) timing characteristics. Be aware

that only DATA is sampled on both edges of the clock (not applicable to CMD).

SD1

SD2

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

Figure 23. eMMC5.1/SD3.0 (DDR) timing

Table 54. SD3.0/eMMC5.1 (DDR) interface timing specification[1],[2]

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (eMMC5.1 DDR)

fPP

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

2.8

6.8

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

2.4

—

SD4

uSDHC Input Hold Time

tIH

1.5

—

[1] Input timing assumes an input signal slew rate of 3 ns (20%/80%).

[2] Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm, unterminated, 5-inch microstrip trace

on standard FR4 (3.3 pF/inch), (25 pF total with margin). For best signal integrity, the series resistance in the transmission line should be equal to the selected

RDSON of the I/O pad output driver.

4.12.1.3 HS400 DDR AC timing

Figure 24 depicts the timing of HS400 mode, Table 55 and Table 56 list the HS400 timing characteristics. Be aware that only data

is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for HS400 mode is the same as CMD

input/output timing for SDR104 mode. Check SD5, SD6, and SD7 parameters in Table 59 and Table 60 for HS400 mode.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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