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IMX93CEC Datasheet(PDF) 86 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 123 page  Table 102. 11 x 11 mm functional contact assignment Ball name 11 x 11 ball Power group Ball Types Default setting Default modes Default function Status while reset is asserted ADC_IN0 B19 VDD_ANA0_1P8 ANALOG — — Input without PU[1] / PD[2] ADC_IN1 A20 VDD_ANA0_1P8 ANALOG — — Input without PU / PD ADC_IN2 B20 VDD_ANA0_1P8 ANALOG — — Input without PU / PD ADC_IN3 B21 VDD_ANA0_1P8 ANALOG — — Input without PU / PD CCM_CLKO1 AA2 NVCC_WAKEUP GPIO Alt0 CCMSRCGPCMIX.CLK01 Output low CCM_CLKO2 Y3 NVCC_WAKEUP GPIO Alt0 CCMSRCGPCMIX.CLK02 Output low CCM_CLKO3 U4 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[28] Input with PD CCM_CLKO4 V4 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[29] Input with PD CLKIN1 B17 VDD_ANA0_1P8 ANALOG — — Input without PU / PD CLKIN2 A18 VDD_ANA0_1P8 ANALOG — — Input without PU / PD DAP_TCLK_SWCLK Y1 NVCC_WAKEUP GPIO Alt0 DAP.TCLK_SWCLK Input with PD DAP_TDI W1 NVCC_WAKEUP GPIO Alt0 DAP.TDI Input with PU DAP_TDO_TRACESW O Y2 NVCC_WAKEUP GPIO Alt0 DAP.TDO_TRACESWO Input without PU/PD DAP_TMS_SWDIO W2 NVCC_WAKEUP GPIO Alt0 DAP.TMS_SWDIO Input with PU DRAM_CA0_A H2 VDDQ_DDR DDR — — — DRAM_CA1_A G1 VDDQ_DDR DDR — — — DRAM_CA2_A F2 VDDQ_DDR DDR — — — DRAM_CA3_A E1 VDDQ_DDR DDR — — — DRAM_CA4_A E2 VDDQ_DDR DDR — — — DRAM_CA5_A D1 VDDQ_DDR DDR — — — Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 86 / 123 |
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