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Table 82. FlexSPI input timing in SDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0x3 (case A2) (Low drive mode)

Symbol

Parameter

Value

Unit

Min

Max

—

Frequency of operation

—

133

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-2

TSCKD

FLEXSPI_SCLK

FLEXSPI_DATA[7:0]

FLEXSPI_DQS

Internal Sample Clock

TSCKD

TSCKDQS

Figure 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)

Note:

Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK rising edge. The

FlexSPI controller samples read data on a half cycle delayed DQS falling edge.

4.12.9.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 83. FlexSPI input timing in DDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0x0 (Nominal, Overdrive, and Low

drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

MHz

Setup time for incoming data

—

Hold time for incoming data

—

Table 84. FlexSPI input timing in DDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0x1 (Nominal and Overdrive mode)

[1]

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[2]

—

MHz

Setup time for incoming data

—

Hold time for incoming data

—

[1] These timing specifications are valid only for 1.8 V nominal I/O pad supply voltage. For 3.3 V I/O supply, see Table 85

[2] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

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Product data sheet

Rev. 7 — 12 February 2026

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