IMX93CEC datasheet(72/123 Pages) NXP

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[1] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

Table 76. FlexSPI input timing in SDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0X0 (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation

—

MHz

Setup time for incoming data

—

Hold time for incoming data

—

Table 77. FlexSPI input timing in SDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0X1 (Nominal and Overdrive mode)

[1]

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[2]

—

166

MHz

Setup time for incoming data

—

Hold time for incoming data

—

[1] These timing specifications are valid only for 1.8 V nominal I/O pad supply voltage. For 3.3 V I/O supply, see Table 78.

[2] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

Table 78. FlexSPI input timing in SDR mode where FlexSPI

n_MCR0[RXCLKSRC] = 0X1 (Low drive mode)

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation[1]

—

100

MHz

Setup time for incoming data

—

Hold time for incoming data

—

[1] The maximum frequency supported is 56 MHz when NVCC_xxxx operating at 3.3 V.

FLEXSPI_SCLK

FLEXSPI_DATA[7:0]

Internal Sample Clock

Figure 43. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1

Note:

Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data

on the falling edge.

4.12.9.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

• A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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