IMX93CEC datasheet(28/123 Pages) NXP

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Table 25. GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage

VOH (1.8 V)

DSE = X1, IOH = 1.1 mA DSE =

X6, IOH = 6.6 mA

0.8 x

NVCC_xxx

—

NVCC_xxx

VOH (3.3 V) DSE = X1, IOH = 2 mA DSE = X4,

IOH = 8 mA

0.8 x

NVCC_xxx

—

NVCC_xxx

Low-level output voltage

VOL (1.8 V)

DSE = X1, IOL = 1.1 mA DSE =

X6, IOL = 6.6 mA

—

0.2 x

NVCC_xxx

VOL (3.3 V)

DSE = X1, IOL = 2 mA DSE = X4,

IOL = 8 mA

—

0.2 x

NVCC_xxx

Low-level input voltage

VIL

NVCC_xxx = 1.65 - 3.465 V; Temp

= -40 to 125°C

—

0.3 x

NVCC_xxx

High-level input voltage

VIH

NVCC_xxx = 1.65 - 3.465 V;

Temp = -40 to 125°C

0.7 x

NVCC_xxx

—

NVCC_xxx

Pull-down resistor

Rpd3.3v

NVCC_xxx = 3.0 - 3.465 V; Temp =

-40 to 125°C

KΩ

Pull-up resistor

Rpu3.3v

KΩ

Pull-down resistor

Rpd1.8v

NVCC_xxx = 1.65 - 1.95 V; Temp

= -40 to 125°C

KΩ

Pull-up resistor

Rpu1.8v

KΩ

Note: For GPIO pads, when the supplies are ramp-up or/and below operating level, the pad state values are undefined.

Note: For PHY pads, the PAD state values are undefined before POR_B is asserted.

Table 26. Additional leakage parameters

Parameter

Symbol

Condition

Min

Max

Unit

Leakage high

IIH

Non-PHY I/O, 1.65 V - 3.465 V, Temp =

-40°C to 125°C | pad = VDDIO

[1]

-5

µA

Leakage low

IIL

Non-PHY I/O, 1.65 V - 3.465 V, Temp =

-40°C to 125°C | pad = VSS

[1]

-5

[1] This specification does not apply to PHY, ANALOG, TAMPER0, TAMPER1 I/Os, PMIC_ON_REQ, and PMIC_STBY_REQ.

4.5.2 DDR I/O DC electrical characteristics

The DDR I/O pads support LPDDR4/LPDDR4X operational modes. The Double Data Rate Controller (DDRC) is compliant with

JEDEC-compliant SDRAMs.

DDRC operation is contingent upon the board’s DDR design adherence to the DDR design and layout requirements stated in the

hardware development guide for the i.MX 93 application processors.

4.5.3 LVDS DC parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, "Electrical Characteristics of Low

Voltage Differential Signaling (LVDS) Interface Circuits" for details.

NXP Semiconductors

IMX93CEC

i.MX 93 Applications Processors Data Sheet for Commercial Products

IMX93CEC

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 12 February 2026

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